Datasheet

Section 20 Power-Down Modes
Rev.7.00 Dec. 24, 2008 Page 613 of 698
REJ09B0074-0700
20.1.2 Timer Control/Status Register (TCSR_1)
TCSR_1 controls the operation in power-down mode transition.
Bit Bit Name Initial Value R/W Description
7 to 5 ⎯ All 0 ⎯ Reserved
The write value should always be 0.
4 PSS 0 R/W Prescaler Select
0: When the SLEEP instruction is executed in high-
speed mode or medium-speed mode, operation
shifts to sleep mode or software standby mode.
1: When the SLEEP instruction is executed in high-
speed mode or medium-speed mode, operation
shifts to sleep mode, watch mode, or subactive
mode.
When the SLEEP instruction is executed in
subactive mode, operation shifts to subsleep
mode, watch mode, or high-speed mode
TCSR_1 differs from other registers in being more
difficult to write to. The procedures for writing to
and reading this register are given below.
Write:
TCSR_1 must be written to by a word transfer
instruction. The upper byte of the written word must
contain H′A5 and the lower byte must contain the
write data. (When the PSS bit is set to 1, the upper
byte of the written word must contain H'A510.)
Read:
TCSR_1 is read by the same procedure as for the
general registers.
3 to 0 — All 0 — Reserved
The write value should always be 0.