Datasheet

Section 20 Power-Down Modes
Rev.7.00 Dec. 24, 2008 Page 620 of 698
REJ09B0074-0700
20.4.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode
Bits STS2 to STS0 in SBYCR should be set as described below.
• Using a Crystal Oscillator:
Set bits STS2 to STS0 so that the standby time is at least t
OSC2
ms (the oscillation stabilization
time).
Table 20.3 shows the standby times for different operating frequencies and settings of bits
STS2 to STS0.
• Using an External Clock
Set bits STS2 to STS0 as any value. Usually, minimum value is recommended. A standby time
of 100 μs or longer (flash memory power supply stabilization time) should be used in the F-
ZTAT version.
Table 20.3 Oscillation Stabilization Time Settings
STS2 STS1 STS0 Standby Time 24MHz 20MHz 16MHz 13MHz 10MHz 8MHz 6MHz 4MHz 2MHz Unit
0 0 0 8192 states 0.34 0.41 0.51 0.63 0.82 1.0 1.4 2.0
4.1 ms
1 16384 states 0.68 0.82 1.0 1.3 1.6 2.0 2.7 4.1 8.2
1 0 32768 states 1.4 1.6 2.0 2.5 3.3 4.1 5.5 8.2 16.4
1 65536 states 2.7 3.3 4.1 5.0 6.6 8.2 10.9 16.4 32.8
1 0 0 131072 states 5.5 6.6 8.2 10.1 13.1 16.4 21.8 32.8 65.5
1 262144 states 10.9 13.1 16.4 20.2 26.2 32.8 43.7 65.5 131.1
1 0 2048 states 0.09 0.10 0.13 0.16 0.20 0.26 0.34 0.51 1.0
1 16 states 0.67 0.80 1.0 1.2 1.6 2.0 2.7 4.0 8.0 µs
: Recommended time setting (For conditions, see t
OSC2
in table 22.4.)
20.4.4 Software Standby Mode Application Example
Figure 20.4 shows an example in which a transition is made to software standby mode at the
falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI
pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is then cleared at the rising edge on the NMI pin.