The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 H8S/2215 Group User's Manual: Hardware Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series H8S/2215 H8S/2215R H8S/2215T H8S/2215C HD64F2215 HD64F2215U HD6432215B HD6432215C HD64F2215R HD64F2215RU HD64F2215T HD64F2215TU HD64F2215CU Rev.9.
Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Main Revisions for This Edition The history of revisions is a summary of sections that have been revised and sections that have been added to earlier versions. This does not include all of the revised contents. For details, confirm by referring to the main description of this manual. 5. Contents 6. Overview 7. Table of Contents 8.
Preface This LSI is a high-performance microcomputer (MCU) made up of the H8S/2000 CPU with Renesas’ original architecture as its core, and the peripheral functions required to configure a system. The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a 16-Mbyte linear address space.
• In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. • In order to understand the details of the CPU’s functions Read the H8S/2600 Series, H8S/2000 Series Software Manual.
Main Revisions for This Edition Item Page Revision (See Manual for Details) 1.5 Pin Functions 17 Table amended Pin No. 2.6.1 Table of 45 Instructions Classified by Function Type Symbol TFP-120, BP-112, TFP-120V BP-112V I/O Boundary scan TRST 109 B5 Function Input Reset pin for the TAP controller Perform pin processing even when the boundary scan function is not used. For details, see 14.5, Usage Notes. Table amended Instruction Size* Function BAND B C ∧ (
Item Page Revision (See Manual for Details) 15.3.2 USB Control Register (UCTLR) 505 Table amended Bit Bit Name Initial Value R/W 1 UIFRST 1 R/W Description USB Interface Software Reset Controls USB module internal reset. When the UIFRST bit is set to 1, the USB internal modules other than UCTLR, UIER3, and the CK48 READY bit of UIFR3 are all reset.
Item Page 24.6 A/D Conversion 749 Characteristics Table 24.9 A/D Conversion Characteristics Revision (See Manual for Details) Conditions added Conditions: VCC = PLLVCC = DrVCC = 2.7 V to 3.6 V*, AVCC = 2.7 V to 3.6 V*, Vref = 2.7 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 13 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Note added Note: * AN0 and AN1 can be used only when VCC = AVCC. 25.
Item Page Revision (See Manual for Details) 26.3 DC Characteristics 784 Table amended Item Table 26.2 DC Characteristics Input high voltage 786 Symbol Min. 6 Ports* 4 and 9 VIH VCC × 0.8 Typ. — Test Unit Conditions 6 * AVCC + 0.3 V Max. Note added 3. ICC (max.) = 1.0 (mA) + 0.67 (mA/(MHz x V)) × VCC × f (normal operation, USB halted) ICC (max.) = 1.0 (mA) + 0.85 (mA/(MHz x V)) × VCC × f (normal operation, USB operating, f = 16 MHz : PLL 3 × multiplication) ICC (max.) = 1.0 (mA) + 0.
Item Page Revision (See Manual for Details) 27.3 DC Characteristics 811 Note added Table 27.2 DC Characteristics 3. ICC (max.) = 1.0 (mA) + 0.67 (mA/(MHz x V)) × VCC × f (normal operation, USB halted) ICC (max.) = 1.0 (mA) + 0.85 (mA/(MHz x V)) × VCC × f (normal operation, USB operating, f = 16 MHz : PLL 3 × multiplication) ICC (max.) = 1.0 (mA) + 0.72 (mA/(MHz x V)) × VCC × f (normal operation, USB operating, f = 24 MHz : PLL 2 × multiplication) ICC (max.) = 1.0 (mA) + 0.
All trademarks and registered trademarks are the property of their respective owners. Page xii of liv REJ09B0140-0900 Rev. 9.
Contents Section 1 Overview .................................................................................................................. 1 1.1 1.2 1.3 1.4 1.5 Overview............................................................................................................................... 1 Internal Block Diagram......................................................................................................... 3 Pin Arrangement ..............................................................
2.8 2.9 Processing States ................................................................................................................ 56 Usage Notes ........................................................................................................................ 58 2.9.1 Note on TAS Instruction Usage .......................................................................... 58 2.9.2 STM/LTM Instruction Usage ............................................................................. 58 2.9.
5.4 5.5 5.6 5.7 5.3.2 IRQ Enable Register (IER) ................................................................................. 88 5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL).................................... 89 5.3.4 IRQ Status Register (ISR)................................................................................... 91 Interrupt Sources................................................................................................................. 92 5.4.1 External Interrupts ..
6.6 6.7 6.8 6.9 6.10 6.11 Basic Bus Interface ........................................................................................................... 127 6.6.1 Data Size and Data Alignment.......................................................................... 127 6.6.2 Valid Strobes .................................................................................................... 128 6.6.3 Basic Timing..............................................................................................
7.5 7.6 7.4.13 Forced Termination of DMAC Operation......................................................... 199 7.4.14 Clearing Full Address Mode ............................................................................. 200 Interrupts........................................................................................................................... 201 Usage Notes ...................................................................................................................... 202 7.6.
8.8.2 8.8.3 8.8.4 On-Chip RAM .................................................................................................. 227 DTCE Bit Setting.............................................................................................. 227 DMAC Transfer End Interrupt.......................................................................... 227 Section 9 I/O Ports ............................................................................................................... 229 9.1 9.2 9.3 9.
9.8 9.9 9.10 9.11 9.12 9.13 9.7.5 Pin Functions .................................................................................................... 256 9.7.6 Port B Input Pull-Up MOS Function ................................................................ 258 Port C ................................................................................................................................ 258 9.8.1 Port C Data Direction Register (PCDDR) ........................................................
10.4 10.5 10.6 10.7 10.8 10.3.2 Timer Mode Register (TMDR) ......................................................................... 293 10.3.3 Timer I/O Control Register (TIOR) .................................................................. 295 10.3.4 Timer Interrupt Enable Register (TIER) ........................................................... 304 10.3.5 Timer Status Register (TSR)............................................................................. 306 10.3.6 Timer Counter (TCNT).....
11.6 11.7 11.8 11.5.2 Setting of Compare Match Flags CMFA and CMFB ....................................... 358 11.5.3 Timer Output Timing........................................................................................ 358 11.5.4 Timing of Compare Match Clear ...................................................................... 359 11.5.5 Timing of TCNT External Reset....................................................................... 359 11.5.6 Timing of Overflow Flag (OVF) Setting ..........
Section 13 Serial Communication Interface ................................................................. 381 13.1 13.2 13.3 13.4 13.5 13.6 13.7 Features............................................................................................................................. 381 13.1.1 Block Diagram.................................................................................................. 383 Input/Output Pins..................................................................................
13.7.3 Clock................................................................................................................. 449 13.7.4 Block Transfer Mode ........................................................................................ 449 13.7.5 Receive Data Sampling Timing and Reception Margin.................................... 450 13.7.6 Initialization ...................................................................................................... 451 13.7.
15.3.3 15.3.4 15.3.5 15.3.6 15.3.7 15.3.8 15.3.9 15.3.10 15.3.11 15.3.12 15.3.13 15.3.14 15.3.15 15.3.16 15.3.17 15.3.18 15.3.19 15.3.20 15.3.21 15.3.22 15.3.23 15.3.24 15.3.25 15.3.26 15.3.27 15.3.28 15.3.29 15.3.30 15.3.31 15.3.32 15.3.33 15.3.34 15.3.35 15.3.36 15.3.37 15.3.38 Page xxiv of liv USB DMAC Transfer Request Register (UDMAR)......................................... 506 USB Device Resume Register (UDRR)............................................................
15.3.39 15.3.40 15.4 15.5 15.6 15.7 15.8 15.9 USB Interrupt Select Register 1 (UISR1) (Only in H8S/2215) ........................ 533 USB Interrupt Select Register 1 (UISR1) (Only in H8S/2215R, H8S/2215T and H8S/2215C) ......................................... 533 15.3.41 USB Interrupt Select Register 2 (UISR2) (Only in H8S/2215) ........................ 534 15.3.42 USB Interrupt Select Register 2 (UISR2) (Only in H8S/2215R, H8S/2215T and H8S/2215C) ......................................... 534 15.3.
15.9.6 15.9.7 15.9.8 15.9.9 15.9.10 15.9.11 15.9.12 15.9.13 15.9.14 15.9.15 15.9.16 15.9.17 15.9.18 Data Register Overread or Overwrite ............................................................... 592 EP3o Isochronous Transfer............................................................................... 593 Reset ................................................................................................................. 595 EP0 Interrupt Assignment..................................................
17.3 17.4 17.5 Register Description.......................................................................................................... 620 17.3.1 D/A Data Register (DADR) .............................................................................. 620 17.3.2 D/A Control Register (DACR) ......................................................................... 621 Operation ..........................................................................................................................
Section 20 Masked ROM ................................................................................................... 665 20.1 Features............................................................................................................................. 665 Section 21 Clock Pulse Generator ................................................................................... 667 21.1 21.2 21.3 21.4 21.5 21.6 21.7 21.8 Register Descriptions.......................................................
22.5 22.6 22.7 22.8 Hardware Standby Mode .................................................................................................. 693 22.5.1 Transition to Hardware Standby Mode ............................................................. 693 22.5.2 Clearing Hardware Standby Mode.................................................................... 693 22.5.3 Hardware Standby Mode Timing...................................................................... 694 22.5.
25.5 25.6 25.7 25.8 25.9 25.4.2 Control Signal Timing ...................................................................................... 761 25.4.3 Bus Timing ....................................................................................................... 763 25.4.4 Timing of On-Chip Supporting Modules.......................................................... 770 USB Characteristics..........................................................................................................
A. B. C. I/O Port States in Each Processing State........................................................................... 835 Product Model Lineup ...................................................................................................... 839 Package Dimensions ......................................................................................................... 840 Index ......................................................................................................................
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Figures Section 1 Overview Figure 1.1 Internal Block Diagram ................................................................................................. 3 Figure 1.2 Pin Arrangement (TFP-120, TFP-120V)....................................................................... 4 Figure 1.3 Pin Arrangement (BP-112, BP-112V)........................................................................... 5 Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode)...............................................
Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Figure 5.7 Figure 5.8 Block Diagram of IRQn Interrupts.............................................................................. 92 Set Timing for IRQnF ................................................................................................. 93 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0..... 97 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2.....
Figure 7.5 Operation in Idle Mode ............................................................................................. 176 Figure 7.6 Example of Idle Mode Setting Procedure.................................................................. 177 Figure 7.7 Operation in Repeat Mode......................................................................................... 179 Figure 7.8 Example of Repeat Mode Setting Procedure............................................................. 180 Figure 7.
Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.1 Block Diagram of TPU............................................................................................ 284 Figure 10.2 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)] ...................... 311 Figure 10.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)].................. 312 Figure 10.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)] ............. 312 Figure 10.
Figure 10.39 Figure 10.40 Figure 10.41 Figure 10.42 Figure 10.43 Figure 10.44 Figure 10.45 Figure 10.46 Figure 10.47 Figure 10.48 Figure 10.49 Figure 10.50 Figure 10.51 Figure 10.52 Figure 10.53 TGI Interrupt Timing (Input Capture) ................................................................... 339 TCIV Interrupt Setting Timing.............................................................................. 340 TCIU Interrupt Setting Timing..................................................................
Section 13 Serial Communication Interface Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Figure 13.4 Figure 13.5 Figure 13.5 Figure 13.5 Figure 13.5 Figure 13.6 Block Diagram of SCI_0 (H8S/2215) ..................................................................... 383 Block Diagram of SCI_0 (H8S/2215R, H8S/2215T and H8S/2215C).................... 384 Block Diagram of SCI_1 and SCI_2 .......................................................................
Figure 13.28 Inverse Convention (SDIR = SINV = O/E = 1)..................................................... 449 Figure 13.29 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Transfer Rate) ..................................................... 450 Figure 13.30 Retransfer Operation in SCI Transmit Mode......................................................... 453 Figure 13.31 TEND Flag Generation Timing in Transmission Operation.................................. 453 Figure 13.
Figure 15.9 Example Flowchart of Suspend and Resume Interrupt Processing ......................... 553 Figure 15.10 Example Flowchart of Suspend and Remote-Wakeup Operations........................ 554 Figure 15.11 Example Flowchart of Remote-Wakeup Interrupt Processing .............................. 555 Figure 15.12 Control Transfer Stage Configuration ................................................................... 556 Figure 15.13 Setup Stage Operation .................................................
Figure 16.5 A/D Conversion Timing .......................................................................................... 611 Figure 16.6 External Trigger Input Timing ................................................................................ 612 Figure 16.7 A/D Conversion Precision Definitions (1) .............................................................. 614 Figure 16.8 A/D Conversion Precision Definitions (2) .............................................................. 614 Figure 16.
Figure 21.6 External Clock Input Timing................................................................................... 674 Figure 21.7 Connection of Ceramic Resonator........................................................................... 675 Figure 21.8 Connection of Ceramic Resonator........................................................................... 675 Figure 21.9 48-MHz External Clock Input Timing .................................................................... 676 Figure 21.
Figure 24.22 Figure 24.23 Figure 24.24 Figure 24.25 Boundary Scan TRST Input Timing (At Reset Hold) ........................................... 745 Boundary Scan Data Transmission Timing........................................................... 746 Data Signal Timing ............................................................................................... 748 Test Load Circuit...................................................................................................
Figure 26.8 Basic Bus Timing (Three-State Access).................................................................. 794 Figure 26.9 Basic Bus Timing (Three-State Access with One Wait State) ................................ 795 Figure 26.10 Burst ROM Access Timing (Two-State Access)................................................... 796 Figure 26.11 External Bus Release Timing ................................................................................ 797 Figure 26.12 I/O Port Input/Output Timing.......
Figure 27.21 Figure 27.22 Figure 27.23 Figure 27.24 Figure 27.25 Boundary Scan TCK Input Timing ....................................................................... 827 Boundary Scan TRST Input Timing (At Reset Hold) ........................................... 827 Boundary Scan Data Transmission Timing........................................................... 828 Data Signal Timing ............................................................................................... 830 Test Load Circuit.....
Page xlvi of liv REJ09B0140-0900 Rev. 9.
Tables Section 2 CPU Table 2.1 Table 2.2 Table 2.3 Table 2.4 Table 2.4 Table 2.5 Table 2.6 Table 2.7 Table 2.7 Table 2.8 Table 2.9 Table 2.10 Table 2.11 Table 2.12 Table 2.13 Table 2.13 Instruction Classification........................................................................................... 39 Operation Notation.................................................................................................... 40 Data Transfer Instructions .......................................................
Section 6 Bus Controller Table 6.1 Table 6.2 Table 6.3 Table 6.4 Table 6.5 Pin Configuration .................................................................................................... 111 Bus Specifications for Each Area (Basic Bus Interface) ......................................... 123 Data Buses Used and Valid Strobes ........................................................................ 128 Pin States in Idle Cycle ............................................................................
Table 9.7 Table 9.8 Table 9.9 Table 9.10 Table 9.11 Table 9.12 Table 9.13 Table 9.14 Table 9.15 Table 9.16 Table 9.17 Table 9.18 Table 9.19 Table 9.20 Table 9.21 Table 9.22 Table 9.23 Table 9.24 Table 9.25 Table 9.26 Table 9.27 Table 9.28 Table 9.29 Table 9.30 Table 9.31 Table 9.32 Table 9.33 Table 9.34 Table 9.35 Table 9.36 Table 9.37 Table 9.38 Table 9.39 Table 9.40 Table 9.41 Table 9.42 Table 9.43 Table 9.44 Table 9.45 Table 9.46 P12 Pin Function .........................................................
Table 9.47 Table 9.48 Table 9.49 Table 9.50 Table 9.51 Table 9.52 Table 9.53 Table 9.54 Table 9.55 Table 9.56 Table 9.57 Table 9.58 Table 9.59 Table 9.60 Table 9.61 Table 9.62 Table 9.63 Table 9.64 Table 9.65 Table 9.66 Table 9.67 Table 9.68 Table 9.69 Table 9.70 Table 9.71 Table 9.72 Table 9.73 Table 9.74 Table 9.75 Table 9.76 PD5 Pin Function .................................................................................................... 266 PD4 Pin Function ..........................................
Table 10.9 Table 10.10 Table 10.11 Table 10.12 Table 10.13 Table 10.14 Table 10.15 Table 10.16 Table 10.17 Table 10.18 Table 10.19 Table 10.20 Table 10.21 Table 10.22 Table 10.23 Table 10.24 TIORH_0 (channel 0).............................................................................................. 296 TIORH_0 (channel 0).............................................................................................. 297 TIORL_0 (channel 0) ................................................................
Table 13.12 SCI Interrupt Sources.............................................................................................. 462 Table 13.13 Interrupt Sources in Smart Card Interface Mode .................................................... 463 Section 14 Boundary Scan Function Table 14.1 Table 14.2 Table 14.3 Table 14.4 Pin Configuration .................................................................................................... 473 Instruction configuration ...................................
Table 19.8 Table 19.9 Flash Memory Operating States .............................................................................. 658 Registers Present in F-ZTAT Version but Absent in Masked ROM Version ......... 664 Section 21 Clock Pulse Generator Table 21.1 Table 21.2 Table 21.3 Table 21.4 Table 21.5 Table 21.6 List of Suitable Resonators...................................................................................... 671 Damping Resistance Value .................................................
Table 25.8 USB Characteristics (USD+ and USD- pins) when On-Chip USB Transceiver Is Used ........................................................................................................................ 776 Table 25.9 A/D Conversion Characteristics.............................................................................. 778 Table 25.10 D/A Conversion Characteristics.............................................................................. 779 Table 25.11 Flash Memory Characteristics........
H8S/2215 Group Section 1 Overview Section 1 Overview 1.
H8S/2215 Group Section 1 Overview • General I/O ports Modes 4 and 5 Mode 6 Mode 7 ⎯ I/O pins: 41 41 68 ⎯ Input-only pins: 15 23 7 • Supports various power-down states • Compact package Package (Code) Body Size Pin Pitch Remarks TQFP-120 TFP-120, TFP-120V* 14.0 × 14.0 mm 0.4 mm ⎯ P-LFBGA-112 BP-112, BP-112V* 10.0 × 10.0 mm 0.8 mm ⎯ Note: * Page 2 of 846 TFP-120V and BP-120V only for H8S/2215C. REJ09B0140-0900 Rev. 9.
H8S/2215 Group PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 Internal Block Diagram VCC VCC VSS VSS DrVCC DrVSS TDO TDI TCK TMS TRST EMLE*2 1.
H8S/2215 Group Section 1 Overview Pin Arrangement 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P32/CSK0/IRQ4 P31/RxD0 P30/TxD0 PF0/BREQ/IRQ2 PF1/BACK PF2/WAIT NC PF3/LWR/ADTRG/IRQ3 NC PF4/HWR PF5/RD PF6/AS PF7/φ MD2 EXTAL VCC XTAL VSS RES STBY NMI FWE*1 MD1 MD0 EXTAL48 XTAL48 PLLVCC PLLCAP PLLVSS VSS 1.
H8S/2215 Group 11 10 Section 1 Overview NC P31/RxD0 PF1/BACK PF4/HWR P34/RxD1 P33/TxD1 P30/TxD0 PF2/WAIT PF7/φ VCC RES FWE*1 PF6/AS EXTAL VSS MD1 XTAL48 PLLVSS USD- EXTAL48 PLLCAP NC 9 P74/ MRES P36 (PUPD+) P32/ SCK0/ IRQ4 PF0/ BREQ/ IRQ2 PF5/RD XTAL STBY MD0 DrVSS USD+ UBPM 8 P71/CS5 P72/ TMO0/ CS6 P73/ TMO1/ CS7 P35/ SCK1/ IRQ5 PF3/ LWR/ ADTRG/ IRQ3 MD2 NMI PLLVCC DrVCC VBUS AVCC 7 PG1/ PG2/CS2 CS3/IRQ7 PG0 P70/ TMRI01/ TMCI01/ CS4 USPND Vref 6 PG4/CS0 TD
H8S/2215 Group Section 1 Overview 1.4 Pin Functions in Each Operating Mode Pin No.
H8S/2215 Group Section 1 Overview Pin No.
H8S/2215 Group Section 1 Overview Pin No.
H8S/2215 Group Section 1 Overview Pin No.
H8S/2215 Group Section 1 Overview Pin No.
H8S/2215 Group 1.5 Section 1 Overview Pin Functions Pin No. Type Symbol Power Supply VCC VSS TFP-120, BP-112, TFP-120V BP-112V I/O 10 E4 75 F11 12 61 73 E1 Function Input Power supply pins. Connect all these pins to the system power supply. Input Ground pins. Connect all these pins to the system power supply (0 V). G10 PLLVCC 64 H8 Input Power supply pin for internal PLL oscillator. Connect this pin to the system power supply.
H8S/2215 Group Section 1 Overview Pin No. Type Symbol TFP-120, BP-112, TFP-120V BP-112V I/O System Control RES 72 G11 Input Reset input pin. When this pin is driven low, the chip is reset. STBY 71 G9 Input When this pin is driven low, a transition is made to hardware standby mode. MRES 96 A9 Input When this pin is driven low, a transition is made to manual reset mode.
H8S/2215 Group Section 1 Overview Pin No. Type Symbol TFP-120, BP-112, TFP-120V BP-112V I/O Function Address bus A23 38 K4 These pins output an address. A22 37 J4 A21 36 L3 A20 35 K3 A19 33 H4 A18 32 L2 A17 31 K2 A16 30 J3 A15 29 K1 A14 28 J2 A13 27 H3 A12 26 J1 A11 25 H2 A10 23 G4 A9 21 H1 A8 20 G3 A7 19 G2 A6 18 G1 A5 17 F4 A4 16 F2 A3 15 F1 A2 14 F3 A1 13 E2 A0 11 E3 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 1 Overview Pin No. Type Symbol TFP-120, BP-112, TFP-120V BP-112V I/O Data bus D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 9 8 7 6 5 4 3 2 120 119 118 117 116 115 113 111 Page 14 of 846 D1 D2 D3 C1 C2 D4 B1 B2 C3 A2 B3 C4 A3 B4 D5 A4 I/O Function These pins constitute a bi-directional data bus. REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 1 Overview Pin No. Type Symbol TFP-120, BP-112, TFP-120V BP-112V I/O Function Bus Control CS7 97 C8 Output Signals for selecting areas 7 to 0. CS6 98 B8 CS5 99 A8 CS4 100 D7 CS3 102 A7 CS2 103 B7 CS1 104 C6 CS0 105 A6 AS 79 E10 Output When this pin is low, it indicates that address output on the address bus is enabled. RD 80 E9 Output When this pin is low, it indicates that the external address space can be read.
H8S/2215 Group Section 1 Overview Pin No. Type Symbol TFP-120, BP-112, TFP-120V BP-112V I/O Function 16-bit timer pulse unit (TPU) TCLKA 37 J4 Input TPU external clock input pins. TCLKB 38 K4 TCLKC 40 H5 TCLKD 42 L5 TIOCA0 35 K3 I/O TIOCB0 36 L3 TIOCC0 37 J4 The TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins. TIOCD0 38 K4 TIOCA1 39 L4 I/O TIOCB1 40 H5 The TGRA_1 to TGRB_1 input capture input/output compare output/PWM output pins.
H8S/2215 Group Section 1 Overview Pin No. Type Symbol TFP-120, BP-112, TFP-120V BP-112V I/O A/D converter AN15 44 J6 AN14 45 L6 AN3 46 K6 AN2 47 H6 AN1 48 L7 AN0 49 K7 ADTRG 83 D/A converter DA1 DA0 Input Analog input pins for the A/D converter. E8 Input Pin for input of an external trigger to start A/D conversion 44 J6 Output 45 L6 Analog output pins for the D/A converter. 51 L8 Input Power supply pin for the A/D and D/A converter.
H8S/2215 Group Section 1 Overview Pin No. Type Symbol TFP-120, BP-112, TFP-120V BP-112V I/O Function USB USD+ 58 K9 I/O USB data input/output pin USD- 59 L10 VBUS 55 K8 Input Connection/disconnection detecting Input/output pin for the USB cable USPND 53 H7 Output USB suspend output This pin is driven high when a transition is made to suspend state.
H8S/2215 Group Section 1 Overview Pin No.
H8S/2215 Group Section 1 Overview Pin No.
H8S/2215 Group Section 1 Overview Pin No. Type Symbol TFP-120, BP-112, TFP-120V BP-112V I/O Function I/O port PF7 78 E11 I/O 8-bit I/O pins PF6 79 E10 PF5 80 E9 PF4 81 D11 PF3 83 E8 PF2 85 D10 PF1 86 C11 I/O 5-bit I/O pins ⎯ NC (No Connection): These pins should not be connected; they should be left open. NC PF0 87 D9 PG4 105 A6 PG3 104 C6 PG2 103 B7 PG1 102 A7 PG0 101 C7 NC 1* A1* 2 2 22 A11 24 L1 34 L11 52 54 82 84 95 112 114 Notes: 1.
Section 1 Overview Page 22 of 846 H8S/2215 Group REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 2 CPU Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending on the product.
H8S/2215 Group Section 2 CPU ⎯ 16 × 16-bit register-register multiply: 20 states ⎯ 32 ÷ 16-bit register-register divide: 20 states • Two CPU operating modes ⎯ Normal mode* ⎯ Advanced mode Note: * Normal mode is not available in this LSI. • Power-down state ⎯ Transition to power-down state by SLEEP instruction ⎯ CPU clock speed selection 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
H8S/2215 Group 2.1.2 Section 2 CPU Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers ⎯ Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been added. • Extended address space ⎯ Normal mode supports the same 64-kbyte address space as the H8/300 CPU. ⎯ Advanced mode supports a maximum 16-Mbyte address space.
H8S/2215 Group Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. • Address Space A maximum address space of 64 kbytes can be accessed.
H8S/2215 Group Section 2 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) EXR*1 SP Reserved*1*3 (SP*2 ) CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used, it is not stored on the stack. 2.
H8S/2215 Group Section 2 CPU 2.2.2 Advanced Mode • Address Space Linear access is provided to a 16-Mbyte maximum address space. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. • Instruction Set All instructions and addressing modes can be used.
H8S/2215 Group Section 2 CPU providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table.
H8S/2215 Group Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.
H8S/2215 Group 2.4 Section 2 CPU Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR).
H8S/2215 Group Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers.
H8S/2215 Group Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is two bytes (one word), so the least significant PC bit is ignored (When an instruction is fetched, the least significant PC bit is regarded as 0). 2.4.3 Extended Control Register (EXR) EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions.
H8S/2215 Group Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.
H8S/2215 Group Section 2 CPU Bit Bit Name Initial Value R/W Description 1 V undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 C undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise.
H8S/2215 Group Section 2 CPU 2.5 Data Formats The H8S/2000 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.9 shows the data formats in general registers.
H8S/2215 Group Section 2 CPU Data Type Register Number Word data Rn Data Image 15 0 MSB Word data 15 0 MSB Longword data LSB En LSB ERn 31 16 15 MSB En 0 Rn LSB Legend: ERn: En: Rn: RnH: RnL: MSB: LSB: General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit Figure 2.9 General Register Data Formats (2) REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
H8S/2215 Group 2.6 Section 2 CPU Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.
H8S/2215 Group Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarizes the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.
H8S/2215 Group Table 2.3 Section 2 CPU Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) 1 Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this LSI. MOVTPE B Cannot be used in this LSI. POP W/L @SP+ → Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.
H8S/2215 Group Section 2 CPU Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* ADD B/W/L SUB Function Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
H8S/2215 Group Section 2 CPU Table 2.4 Arithmetic Operations Instructions (2) Instruction Size* DIVXS B/W 1 Function Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
H8S/2215 Group Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
H8S/2215 Group Section 2 CPU Table 2.7 Bit Manipulation Instructions (1) Instruction Size* BSET B Function 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
H8S/2215 Group Section 2 CPU Table 2.7 Bit Manipulation Instructions (2) Instruction Size* BXOR B Function C ⊕ ( of ) → C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ [∼ ( of ) ] → C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag.
H8S/2215 Group Table 2.8 Section 2 CPU Branch Instructions Instruction Size Function Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below.
H8S/2215 Group Section 2 CPU Table 2.9 System Control Instruction Instruction Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid.
H8S/2215 Group Section 2 CPU Table 2.10 Block Data Transfer Instruction Instruction Size Function EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfer a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. 2.6.
H8S/2215 Group Section 2 CPU (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm, etc. EA(disp) (4) Operation field, effective address extension, and condition field op cc EA(disp) BRA d:16, etc. Figure 2.11 Instruction Formats (Examples) 2.
H8S/2215 Group 2.7.1 Section 2 CPU Register Direct—Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory.
H8S/2215 Group Section 2 CPU For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.
H8S/2215 Group 2.7.8 Section 2 CPU Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode*, H'000000 to H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the branch address is 16 bits long.
H8S/2215 Group Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table 2.13 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct (Rn) rm Operand is general register contents.
H8S/2215 Group Section 2 CPU Table 2.13 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 31 op @aa:16 31 op 0 H'FFFF 24 23 16 15 0 Don't care Sign extension abs @aa:24 31 op 8 7 24 23 Don't care abs 24 23 0 Don't care abs @aa:32 op 31 6 Immediate #xx:8/#xx:16/#xx:32 op 7 0 24 23 Don't care abs Operand is immediate data.
Section 2 CPU 2.8 H8S/2215 Group Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.13 indicates the state transitions. • Reset State In this state the CPU and internal peripheral modules are all initialized and stop. When the RES input goes low all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state.
H8S/2215 Group Section 2 CPU End of bus request Bus request Program execution state SLEEP instruction, SSBY = 0 ion ha nd lin g s bu t of est d es qu En requ e r s Bu Sleep mode st que SLEEP instruction, SSBY = 1 t re up err Int En d o ha f ex nd ce lin pti g on Re qu es tf or ex ce pt Bus-released state Exception handling state RES = High, MRES = High External interrupt request Software standby mode STBY = High, RES = Low Reset state*1 Hardware standby mode*2 Power-down state No
Section 2 CPU 2.9 Usage Notes 2.9.1 Note on TAS Instruction Usage H8S/2215 Group Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas Electronics H8S and H8/300 series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used. 2.9.
H8S/2215 Group Section 2 CPU 1. Read data in byte units 2. Perform bit manipulation on the read data according to the instruction 3. Write data in byte units Example: Using the BCLR instruction to clear pin 14 only of P1DDR for port 1 P1DDR is an 8-bit register that contains write-only bits. It is used to specify the I/O setting of the individual pins in port 1. Reading produces invalid data. Attempting to read from P1DDR returns undefined values.
H8S/2215 Group Section 2 CPU P17 P16 P15 P14 P13 P12 P11 P10 I/O Output Output Output Output Input Input Input Input P1DDR 1 1 1 1 0 0 0 0 Read value 1 1 1 1 1 0 0 0 The BCLR instruction performs bit manipulation on the read value, which is H'F8 in this example. It clears bit 4 to 0.
H8S/2215 Group Section 2 CPU In order to write to a register containing write-only bits, set aside a work area in memory (in onchip RAM, for example) and write the data to be manipulated to it. After accessing and manipulating the data in the work area in memory, write the resulting data to the register containing write-only bits. Figure 2.
H8S/2215 Group Section 2 CPU P17 P16 P15 P14 P13 P12 P11 P10 I/O Output Output Output Output Input Input Input Input P1DDR 1 1 1 1 0 0 0 0 RAM0 1 1 1 1 0 0 0 0 To change pin 14 from an output pin to an input pin, the value of bit 4 in P1DDR must be changed from 1 to 0 (H'F0 to H'E0). Here the BCLR instruction will be used to clear bit 4 in P1DDR to 0.
H8S/2215 Group Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI supports four operating modes (modes 7 to 4). These modes are depending on the setting of mode pins (MD2 to MD0). Modes 6 to 4 are extended modes in which external memory and external peripheral devices can be accessed. In extended modes, each area can be used as 8-bit or 16-bit address space according to the bus controller settings after program execution.
H8S/2215 Group Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to the operating mode. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR is used to monitor the current operating mode of this LSI. Bit Bit Name Initial Value R/W Description 7 — 1 Reserved — This bit is always read as 1 and cannot be modified. 6 to 3 — All 0 — Reserved These bits are always read as 0 and cannot be modified.
H8S/2215 Group Section 3 MCU Operating Modes Bit Bit Name Initial Value R/W Description 7 — 0 Reserved R/W The write value should always be 0. 6 — 0 — Reserved This bit is always read as 0 and cannot be modified. 5 INTM1 0 R/W 4 INTM0 0 R/W These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.6, Interrupt Control Modes and Interrupt Operation.
Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 4 H8S/2215 Group The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Pins P13 to P10, and ports A, B, and C function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. Pins P13 to P11 function as input ports immediately after a reset. Pin 10 and ports A and B function as address (A20 to A8) outputs immediately after a reset.
H8S/2215 Group 3.3.3 Section 3 MCU Operating Modes Mode 6 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Pins P13 to P10, and ports A, B and C function as input ports immediately after a reset. Address (A23 to A8) output can be enabled or disabled by bits AE3 to AE0 in the pin function control register (PFCR) regardless of the corresponding data direction register (DDR) values.
H8S/2215 Group Section 3 MCU Operating Modes 3.3.5 Pin Functions The pin functions of ports 1, and A to F vary depending on the operating mode. Table 3.3 shows the functions in modes 4 to 7. Table 3.
H8S/2215 Group 3.4 Section 3 MCU Operating Modes Memory Map in Each Operating Mode Figures 3.1 to 3.4 show the memory map in each operating mode for HD64F2215, HD64F2215U, HD6432215B, and HD6432215C.
H8S/2215 Group Section 3 MCU Operating Modes ROM: — RAM: 16 kbytes Modes 4 and 5 (advanced extended modes with on-chip ROM disabled) ROM: 128 kbytes RAM: 16 kbytes Mode 6 (advanced extended mode with on-chip ROM enabled) (advanced single-chip mode) H'000000 H'000000 H'000000 ROM: 128 kbytes RAM: 16 kbytes Mode 7*2 On-chip ROM On-chip ROM H'01FFFF H'020000 Reserved External address space H'040000 External address space H'C00000 On-chip USB registers H'C00000 H'E00000 H'E00000 External addres
H8S/2215 Group Section 3 MCU Operating Modes ROM: — RAM: 8 kbytes Modes 4 and 5 (advanced extended modes with on-chip ROM disabled) ROM: 64 kbytes RAM: 8 kbytes Mode 6 (advanced extended mode with on-chip ROM enabled) (advanced single-chip mode) H'000000 H'000000 H'000000 ROM: 64 kbytes RAM: 8 kbytes Mode 7*2 On-chip ROM On-chip ROM H'00FFFF H'010000 Reserved External address space H'040000 External address space H'C00000 On-chip USB registers H'C00000 H'E00000 H'E00000 External address spa
H8S/2215 Group Section 3 MCU Operating Modes ROM: — RAM: 20 kbytes Modes 4 and 5 (advanced extended modes with on-chip ROM disabled) H'000000 ROM: 256 kbytes RAM: 20 kbytes Mode 6 (advanced extended mode with on-chip ROM enabled) H'000000 ROM: 256 kbytes RAM: 20 kbytes Mode 7*2 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM External address space H'03FFFF H'040000 External address space H'C00000 On-chip USB registers H'C00000 H'E00000 H'E00000 External address space*3 H'FF9000
H8S/2215 Group Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode.
H8S/2215 Group Section 4 Exception Handling Table 4.
H8S/2215 Group 4.3 Section 4 Exception Handling Reset A reset has the highest exception priority. When the RES or MRES pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-on. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. This LSI can also be reset by overflow of the watchdog timer. For details, see section 12, Watchdog Timer (WDT).
Section 4 Exception Handling H8S/2215 Group A reset caused by the watchdog timer can also be of either of two types: a power-on reset or a manual reset. When the MRES pin is used, MRES pin input must be enabled by setting the MRESE bit to 1 in SYSCR. 4.3.2 Reset Exception Handling When the RES or MRES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1.
H8S/2215 Group Section 4 Exception Handling Figures 4.1 and 4.2 show examples of the reset sequence.
H8S/2215 Group Section 4 Exception Handling Prefetch of first program Internal processing instruction Vector fetch φ RES, MRES Internal address bus (1) (3) (5) Internal read signal Internal write signal High (2) Internal data bus (1) (3) (2) (4) (5) (6) (4) (6) Reset exception handling vector address (for power-on reset, (1) = H'000000, (3) = H'000002; for manual reset, (1) = H'000004, (3) = H'000006) Start address (contents of reset exception handling vector address) Start address ((5) =
H8S/2215 Group 4.4 Section 4 Exception Handling Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.
H8S/2215 Group Section 4 Exception Handling 4.6 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended control register (EXR) are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared. 3.
H8S/2215 Group 4.7 Section 4 Exception Handling Stack Status after Exception Handling Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. (a) Normal Modes*2 SP EXR Reserved*1 SP CCR CCR CCR*1 CCR*1 PC (16 bits) PC (16 bits) Interrupt control mode 0 Interrupt control mode 2 (b) Advanced Modes SP EXR Reserved*1 SP CCR PC (24 bits) Interrupt control mode 0 CCR PC (24 bits) Interrupt control mode 2 Notes: 1.
H8S/2215 Group Section 4 Exception Handling 4.8 Notes on Use of the Stack When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.
H8S/2215 Group Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes ⎯ Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with IPR ⎯ An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI.
H8S/2215 Group Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1.
H8S/2215 Group 5.2 Section 5 Interrupt Controller Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.
Section 5 Interrupt Controller 5.3 H8S/2215 Group Register Descriptions The interrupt controller has the following registers. For details on the system control register, refer to section 3.2.2, System Control Register (SYSCR).
H8S/2215 Group 5.3.1 Section 5 Interrupt Controller Interrupt Priority Registers A to G, I to K, M (IPRA to IPRG, IPRI to IPRK, IPRM) The IPR registers set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between interrupt sources and IPR settings is shown in table 5.2. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt.
H8S/2215 Group Section 5 Interrupt Controller 5.3.2 IRQ Enable Register (IER) IER controls enabling and disabling of interrupt requests IRQ7 to IRQ0. Bit Bit Name Initial Value R/W Description 7 IRQ7E 0 IRQ7 Enable R/W The IRQ7 interrupt request is enabled when this bit is 1. 6 IRQ6E 0 R/W IRQ6 Enable* The IRQ6 interrupt request is enabled when this bit is 1. 5 IRQ5E 0 R/W IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1.
H8S/2215 Group 5.3.3 Section 5 Interrupt Controller IRQ Sense Control Registers H and L (ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ7, and IRQ5 to IRQ0.
H8S/2215 Group Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 9 IRQ4SCB 0 R/W IRQ4 Sense Control B 8 IRQ4SCA 0 R/W IRQ4 Sense Control A 00: Interrupt request generated at IRQ4 input low level 01: Interrupt request generated at falling edge of IRQ4 input 10: Interrupt request generated at rising edge of IRQ4 input 11: Interrupt request generated at both falling and rising edges of IRQ4 input 7 IRQ3SCB 0 R/W IRQ3 Sense Control B 6 IRQ3SCA 0 R/W IRQ3 Sense Co
H8S/2215 Group Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 1 IRQ0SCB 0 R/W IRQ0 Sense Control B 0 IRQ0SCA 0 R/W IRQ0 Sense Control A 00: Interrupt request generated at IRQ0 input low level 01: Interrupt request generated at falling edge of IRQ0 input 10: Interrupt request generated at rising edge of IRQ0 input 11: Interrupt request generated at both falling and rising edges of IRQ0 input 5.3.
H8S/2215 Group Section 5 Interrupt Controller 5.4 Interrupt Sources 5.4.1 External Interrupts There are eight external interrupts: NMI, IRQ7, and IRQ5 to IRQ0. These interrupts can be used to restore this LSI from software standby mode. IRQ6 is an interrupt only for the on-chip USB. However, IRQ6 is functionally same as IRQ7 restore this LSI from software standby mode. IRQ6 is functionally same as IRQ7 and IRQ5 to IRQ0.
H8S/2215 Group Section 5 Interrupt Controller The setting for IRQnF is shown in figure 5.3. φ IRQn input pin IRQnF Note: n = 7 to 0 Figure 5.3 Set Timing for IRQnF The detection of IRQn interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0; and use the pin as an I/O pin for another function.
H8S/2215 Group Section 5 Interrupt Controller Table 5.
H8S/2215 Group Section 5 Interrupt Controller Interrupt Source Origin of Interrupt Source Vector Number Vector Address* IPR Priority 8-bit timer channel 1 CMIA1 (compare match A) 68 H'0110 IPRI2 to IPRI0 High CMIB1 (compare match B) 69 H'0114 OVI1 (overflow) 70 H'0118 DEND0A 72 H'0120 DEND0B 73 H'0124 DEND1A 74 H'0128 DEND1B 75 H'012C SCI channel 0 ERI0 80 H'0140 RXI0 81 H'0144 TXI0 82 H'0148 TEI0 83 H'014C SCI channel 1 ERI1 84 H'0150 RXI1 85 H'0154 TXI1 8
H8S/2215 Group Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by SYSCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 5.
H8S/2215 Group Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program execution status No Interrupt generated? Yes Yes NMI No No I=0 Hold pending Yes No IRQ0 Yes No IRQ1 Yes EXIRQ1 Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.
H8S/2215 Group Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2.
H8S/2215 Group Section 5 Interrupt Controller Program execution status Interrupt generated? No Yes Yes NMI No Level 7 interrupt? No Yes Mask level 6 or below? Yes No Level 6 interrupt? No Yes Level 1 interrupt? Mask level 5 or below? No No Yes Yes Mask level 0? No Yes Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.
Page 100 of 846 (2) (4) (3) (5) (7) (1) Internal data bus (1) (2) (4) (3) Instruction prefetch address (Not executed.
H8S/2215 Group 5.6.4 Section 5 Interrupt Controller Interrupt Response Times Table 5.4 shows interrupt response times ⎯ the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.
H8S/2215 Group Section 5 Interrupt Controller Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8-Bit Bus Symbol Instruction fetch SI Branch address read SJ Stack manipulation SK 16-Bit Bus Internal Memory 2-State Access 3-State Access 2-State Access 3-State Access 1 4 6 + 2m 2 3+m Legend: m: Number of wait states in an external device access. 5.6.
H8S/2215 Group Section 5 Interrupt Controller Disenable signal Clear signal DMAC Interrupt request IRQ interrupt DTC activation request vector number Selection circuit Select signal Clear signal On-chip supporting module Interrupt source clear signal Control logic DTC DTCER Clear signal DTVECR SWDTE clear signal Determination of priority CPU interrupt request vector number CPU I, I2 to I0 Interrupt controller Figure 5.
H8S/2215 Group Section 5 Interrupt Controller Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 8.4, Location of Register Information and DTC Vector Table. The activation source is directly input to each channel of DMAC.
H8S/2215 Group Section 5 Interrupt Controller 5.7 Usage Notes 5.7.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction.
H8S/2215 Group Section 5 Interrupt Controller 5.7.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.7.
H8S/2215 Group 5.7.6 Section 5 Interrupt Controller NMI Interrupts Usage Notes The NMI interrupt is part of the exception processing performed cooperatively by the LSI's internal interrupt controller and the CPU when the system is operating normally under the specified electrical conditions. No operations, including NMI interrupts, are guaranteed when operation is not normal (runaway status) due to software problems or abnormal input to the LSI's pins.
Section 5 Interrupt Controller Page 108 of 846 H8S/2215 Group REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 6 Bus Controller Section 6 Bus Controller This LSI has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU, DMA controller (DMAC), and data transfer controller (DTC). 6.
H8S/2215 Group Section 6 Bus Controller Figure 6.1 shows a block diagram of the bus controller.
H8S/2215 Group 6.2 Section 6 Bus Controller Input/Output Pins Table 6.1 summarizes the pins of the bus controller. Table 6.1 Pin Configuration Name Symbol I/O Address strove AS Output Strobe signal indicating that address output on address bus is enabled. Read RD Output Strobe signal indicating that external space is being read. High write HWR Output Strobe signal indicating that external space is to be written, and upper half (D15 to D8) of data bus is enabled.
H8S/2215 Group Section 6 Bus Controller 6.3.1 Bus Width Control Register (ABWCR) ABWCR designates each area for either 8-bit access or 16-bit access. ABWCR sets the data bus width for the external memory space. The bus width for on-chip memory and internal I/O registers except for the on-chip USB is fixed regardless of the settings in ABWCR.
H8S/2215 Group 6.3.2 Section 6 Bus Controller Access State Control Register (ASTCR) ASTCR designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers except for the on-chip USB is fixed regardless of the settings in ASTCR.
H8S/2215 Group Section 6 Bus Controller 6.3.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers except for the on-chip USB.
H8S/2215 Group Section 6 Bus Controller Bit Bit Name Initial Value R/W Description 3 W51 1 R/W Area 5 Wait Control 1 and 0 2 W50 1 R/W These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1.
H8S/2215 Group Section 6 Bus Controller • WCRL Bit Bit Name Initial Value R/W Description 7 W31 1 R/W Area 3 Wait Control 1 and 0 6 W30 1 R/W These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1.
H8S/2215 Group Section 6 Bus Controller Bit Bit Name Initial Value R/W Description 1 W01 1 R/W Area 0 Wait Control 1 and 0 0 W00 1 R/W These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1.
H8S/2215 Group Section 6 Bus Controller 6.3.4 Bus Control Register H (BCRH) BCRH selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. Bit Bit Name Initial Value R/W Description 7 ICIS1 1 Idle Cycle Insert 1 R/W Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas.
H8S/2215 Group 6.3.5 Section 6 Bus Controller Bus Control Register L (BCRL) BCRL performs selection of the external bus-released state protocol, and enabling or disabling of WAIT pin input. Bit Bit Name Initial Value R/W 7 BRLE 0 R/W Description Bus release enable Enables or disables external bus release. 0: External bus release is disabled. BREQ and BACK can be used as I/O ports. 1: External bus release is enabled. 6 — 0 R/W Reserved The write value should always be 0.
H8S/2215 Group Section 6 Bus Controller 6.3.6 Pin Function Control Register (PFCR) PFCR performs address output control in external extended mode. Bit Bit Name Initial Value R/W Description 7 to 4 — All 0 Reserved 3 AE3 1/0* R/W Address Output Enable 3 to 0 2 AE2 1/0* R/W 1 AE1 0 R/W 0 AE0 1/0* R/W These bits select enabling or disabling of address outputs A8 to A23 in ROMless extended mode and modes with ROM. Note: R/W The write value should always be 0.
H8S/2215 Group 6.4 Bus Control 6.4.1 Area Divisions Section 6 Bus Controller In advanced mode, the bus controller partitions the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode*, it controls a 64-kbyte address space comprising part of area 0. Figure 6.2 shows an outline of the memory map. Chip select signals (CS0 to CS7 ) can be output for each area. Note: * Not available in this LSI.
H8S/2215 Group Section 6 Bus Controller 6.4.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers except for the on-chip USB are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR.
H8S/2215 Group Table 6.2 Section 6 Bus Controller Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH, WCRL ABWn ASTn Wn1 Wn0 Number of Access Number of Program Wait States Bus Width States 0 0 ⎯ ⎯ 16 1 0 0 1 1 6.4.3 2 0 3 0 1 1 0 2 1 3 0 ⎯ ⎯ 1 0 0 1 Bus Specifications (Basic Bus Interface) 8 2 3 0 0 1 1 0 2 1 3 Bus Interface for Each Area The initial state of each area is basic bus interface, 3-state access space.
H8S/2215 Group Section 6 Bus Controller RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space. When area 7 external space is accessed, the CS7 signal can be output. Only the basic bus interface can be used for the area 7. 6.4.4 Chip Select Signals This LSI can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. Figure 6.
H8S/2215 Group 6.5.1 Section 6 Bus Controller On-Chip Memory (ROM, RAM) Access Timing On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 6.4 shows the on-chip memory access cycle. Figure 6.5 shows the pin states. Bus cycle T1 φ Internal address bus Address Internal read signal Read access Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 6.
H8S/2215 Group Section 6 Bus Controller 6.5.2 On-Chip Peripheral Module Access Timing The on-chip peripheral modules are accessed in two states except on-chip USB. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 6.6 shows the access timing for the on-chip peripheral modules. Figure 6.7 shows the pin states.
H8S/2215 Group 6.5.3 Section 6 Bus Controller External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6.6.3, Basic Timing. 6.6 Basic Bus Interface The basic bus interface enables direct connection of ROM, SRAM, and so on. 6.6.
H8S/2215 Group Section 6 Bus Controller In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Upper data bus Lower data bus D15 D8 D7 D0 Byte size · Even address Byte size · Odd address Word size 1st bus cycle Longword size 2nd bus cycle Figure 6.9 Access Sizes and Data Alignment Control (16-Bit Access Space) 6.6.2 Valid Strobes Table 6.
H8S/2215 Group 6.6.3 Section 6 Bus Controller Basic Timing 8-Bit 2-State Access Space: Figure 6.10 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states cannot be inserted.
H8S/2215 Group Section 6 Bus Controller 8-Bit 3-State Access Space (Except Area 6): Figure 6.11 shows the bus timing for an 8-bit 3state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted.
H8S/2215 Group Section 6 Bus Controller 8-Bit 3-State Access Space (Area 6): Figure 6.12 shows the bus timing for area 6. When area 6 is accessed, the data bus cannot be used. Wait states cannot be inserted. Bus cycle T1 T2 T3 φ Address bus CS6 AS RD Read D15 to D8 Invalid D7 to D0 Invalid HWR LWR (16-bit bus mode) Write LWR (8-bit bus mode) D15 to D8 High High impedance High impedance High impedance D7 to D0 Figure 6.12 Bus Timing for Area 6 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 6 Bus Controller 16-Bit 2-State Access Space: Figures 6.13 to 6.15 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted.
H8S/2215 Group Section 6 Bus Controller Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write High impedance D15 to D8 D7 to D0 Valid Note: n = 0 to 7 Figure 6.14 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 6 Bus Controller Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 7 Figure 6.15 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) Page 134 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 6 Bus Controller 16-Bit 3-State Access Space: Figures 6.16 to 6.18 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted.
H8S/2215 Group Section 6 Bus Controller Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Note: n = 0 to 7 Figure 6.17 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) Page 136 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 6 Bus Controller Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 7 Figure 6.18 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) REJ09B0140-0900 Rev. 9.
Section 6 Bus Controller 6.6.4 H8S/2215 Group Wait Control When accessing external space, this LSI can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings of WCRH and WCRL.
H8S/2215 Group Section 6 Bus Controller Figure 6.19 shows an example of wait state insertion timing. By program wait T1 T2 Tw By WAIT pin Tw Tw T3 φ WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Note: ↓ indicates the timing of WAIT pin sampling. Figure 6.19 Example of Wait State Insertion Timing 6.7 urst ROM Interface With this LSI, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed.
H8S/2215 Group Section 6 Bus Controller 6.7.1 Basic Timing The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state insertion is possible. One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in BCRH. Wait states cannot be inserted.
H8S/2215 Group Section 6 Bus Controller Full access T1 T2 Burst access T1 T1 φ Address bus Only lower address changed CS0 AS RD Data bus Read data Read data Read data Figure 6.21 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 6.7.2 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.6.4, Wait Control.
H8S/2215 Group Section 6 Bus Controller 6.8 Idle Cycle When this LSI accesses external space, it can insert a 1-state idle cycle (TI) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on.
H8S/2215 Group Section 6 Bus Controller Write after Read: If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 6.23 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
H8S/2215 Group Section 6 Bus Controller Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6.24. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals.
H8S/2215 Group 6.9 Section 6 Bus Controller Bus Release This LSI can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. In external extended mode, the bus can be released to an external device by setting the BRLE bit in BCRL to 1. Driving the BREQ pin low issues an external bus request to this LSI.
H8S/2215 Group Section 6 Bus Controller Figure 6.25 shows the timing for transition to the bus-released state. CPU cycle T0 T1 CPU cycle External bus released state T2 φ High impedance Address bus Address High impedance Data bus High impedance CSn High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK Minimum 1 state [1] [1] [2] [3] [4] [5] [2] [3] [4] [5] Low level of BREQ pin is sampled at rise of T2 state.
H8S/2215 Group 6.10 Section 6 Bus Controller Bus Arbitration This LSI has a bus arbiter that arbitrates bus master operations. There are three bus masters, the CPU, DMAC, and DTC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal.
Section 6 Bus Controller H8S/2215 Group • The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. • If the CPU is in sleep mode, it transfers the bus immediately. DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated.
H8S/2215 Group Section 7 DMA Controller (DMAC) Section 7 DMA Controller (DMAC) This LSI has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4 channels. 7.1 Features The features of the DMAC are listed below.
H8S/2215 Group Section 7 DMA Controller (DMAC) A block diagram of the DMAC is shown in figure 7.1.
H8S/2215 Group 7.2 Section 7 DMA Controller (DMAC) Register Configuration The DMAC registers are listed below.
H8S/2215 Group Section 7 DMA Controller (DMAC) Table 7.
H8S/2215 Group 7.3 Register Descriptions 7.3.1 Memory Address Registers (MAR) Section 7 DMA Controller (DMAC) • Short Address Mode MAR is a 32-bit readable/writable register that specifies the transfer source address or destination address. The upper 8 bits of MAR are reserved: they are always read as 0, and cannot be modified. Whether MAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR.
Section 7 DMA Controller (DMAC) 7.3.3 H8S/2215 Group Execute Transfer Count Register (ETCR) • Short Address Mode ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of this register is different for sequential mode and idle mode on the one hand, and for repeat mode on the other. ETCR is not initialized by a reset or in standby mode.
H8S/2215 Group 7.3.4 Section 7 DMA Controller (DMAC) DMA Control Register (DMACR) DMACR controls the operation of each DMAC channel. • Short Address Mode (common to DMACRA and DMACRB) Bit Bit Name Initial Value R/W Description 7 Data Transfer Size DTSZ 0 R/W Selects the size of data to be transferred at one time.
H8S/2215 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 5 Repeat Enable RPE 0 R/W Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed.
H8S/2215 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W Data Transfer Factor 2 DTF2 0 R/W These bits select the data transfer factor (activation source).
H8S/2215 Group Section 7 DMA Controller (DMAC) • Full Address Mode (DMACRA) Bit Bit Name Initial Value R/W Description 15 Data Transfer Size DTSZ 0 R/W Selects the size of data to be transferred at one time.
H8S/2215 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 12 BLKDIR 0 R/W Block Direction 11 BLKE 0 R/W Block Enable These bits specify whether normal mode or block transfer mode is to be used. If block transfer mode is specified, the BLKDIR bit specifies whether the source side or the destination side is to be the block area.
H8S/2215 Group Section 7 DMA Controller (DMAC) • Full Address Mode (DMACRB) Bit Bit Name Initial Value R/W 7 ⎯ 0 R/W Description Reserved Although this bit is readable/writable, only 0 should be written here. 6 DAID 0 R/W Destination Address Increment/Decrement 5 DAIDE 0 R/W Destination Address Increment/Decrement Enable These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed.
H8S/2215 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W 3 2 1 0 DTF3 DTF2 DTF1 DTF0 0 0 0 0 REJ09B0140-0900 Rev. 9.00 Sep 16, 2010 R/W R/W R/W R/W Description Data Transfer Factor These bits select the data transfer factor (activation source).
H8S/2215 Group Section 7 DMA Controller (DMAC) 7.3.5 DMA Band Control Register (DMABCR) DMABCR controls the operation of each DMAC channel. • Short Address Mode Bit Bit Name Initial Value R/W 15 FAE1 0 R/W Description Full Address Enable 1 Specifies whether channel 1 is to be used in short address mode or full address mode. In short address mode, channels 1A and 1B are used as independent channels.
H8S/2215 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 11 DTA1B 0 R/W Data Transfer Acknowledge 10 DTA1A 0 R/W 9 DTA0B 0 R/W 8 DTA0A 0 R/W These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer.
H8S/2215 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 7 DTE1B 0 R/W Data Transfer Enable 6 DTE1A 0 R/W 5 DTE0B 0 R/W 4 DTE0A 0 R/W When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC.
H8S/2215 Group Section 7 DMA Controller (DMAC) • Full Address Mode Bit Bit Name Initial Value R/W Description 15 Full Address Enable 1 FAE1 0 R/W Specifies whether channel 1 is to be used in short address mode or full address mode. In full address mode, channels 1A and 1B are used together as a single channel. 0: Short address mode 1: Full address mode 14 FAE0 0 R/W Full Address Enable 0 Specifies whether channel 0 is to be used in short address mode or full address mode.
H8S/2215 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description Data Transfer Acknowledge Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer.
H8S/2215 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 9 Data Transfer Acknowledge 0 DTA0 0 R/W Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0 data transfer factor setting.
H8S/2215 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description Data Transfer Enable 1 When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU.
H8S/2215 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description Data Transfer Interrupt Enable B Enables or disables an interrupt to the CPU or DTC when transfer is interrupted. If the DTIEB bit is set to 1 when DTME = 0, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC.
H8S/2215 Group Section 7 DMA Controller (DMAC) 7.3.6 DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions so that only specific bits of DMACR for the specific channel and also DMABCR can be changed to prevent inadvertent changes being made to registers other than those for the channel concerned.
H8S/2215 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 7 to — 4 All 0 Reserved 3 0 WE1B — These bits are always read as 0 and cannot be modified. R/W Write Enable 1B Enables or disables writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR by the DTC.
H8S/2215 Group Section 7 DMA Controller (DMAC) MAR, IOAR, and ETCR are always write-enabled regardless of the DMAWER settings. When modifying these registers, the channel for which the modification is to be made should be halted. 7.4 Operation 7.4.1 Transfer Modes Table 7.2 lists the DMAC modes. Table 7.
H8S/2215 Group 7.4.2 Section 7 DMA Controller (DMAC) Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.3 summarizes register functions in sequential mode. Table 7.
H8S/2215 Group Section 7 DMA Controller (DMAC) Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Note: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N–1)) Where: L = Value set in MAR N = Value set in ETCR Figure 7.3 Operation in Sequential Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends.
H8S/2215 Group Section 7 DMA Controller (DMAC) [1] Set each bit in DMABCRH. Sequential mode setting · Clear the FAE bit to 0 to select short address mode. · Specify enabling or disabling of internal interrupt Set DMABCRH [1] clearing with the DTA bit. [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set transfer source and transfer destination addresses [2] [4] Set each bit in DMACR.
H8S/2215 Group Section 7 DMA Controller (DMAC) 7.4.3 Idle Mode Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.4 summarizes register functions in idle mode. Table 7.
H8S/2215 Group Section 7 DMA Controller (DMAC) Transfer requests (activation sources) consist of A/D conversion end interrupt, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 2 compare match/input capture A interrupts. External requests can be set for channel B only. When the DMAC is used in single address mode, only channel B can be set. Figure 7.6 shows an example of the setting procedure for idle mode. [1] Set ech bit in DMABCRH.
H8S/2215 Group Section 7 DMA Controller (DMAC) 7.4.4 Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues.
H8S/2215 Group Section 7 DMA Controller (DMAC) In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number of transfers. ETCRL is decremented by 1 each time a transfer is executed, and when its value reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR restoration operation is as shown below.
H8S/2215 Group Section 7 DMA Controller (DMAC) Transfer requests (activation sources) consist of A/D conversion end interrupt, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 2 compare match/input capture A interrupts. External requests can be set for channel B only. Figure 7.8 shows an example of the setting procedure for repeat mode. [1] Set each bit in DMABCRH. Repeat mode setting · Clear the FAE bit to 0 to select short address mode.
H8S/2215 Group 7.4.5 Section 7 DMA Controller (DMAC) Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB.
H8S/2215 Group Section 7 DMA Controller (DMAC) Figure 7.9 illustrates operation in normal mode. Address TA Transfer Address TB Address BB Address BA Note: Address TA = LA Address TB = LB Address BA = LA + SAIDE · (–1)SAID · (2DTSZ · (N–1)) Address BB = LB + DAIDE · (–1)DAID · (2DTSZ · (N–1)) LA = Value set in MARA LB = Value set in MARB N = Value set in ETCRA Figure 7.9 Operation in Normal Mode Transfer requests (activation sources) are external requests and auto-requests.
H8S/2215 Group Section 7 DMA Controller (DMAC) Figure 7.10 shows an example of the setting procedure for normal mode. [1] Set each bit in DMABCRH. Normal mode setting · Set the FAE bit to 1 to select full address mode. · Specify enabling or disabling of internal interrupt clearing with the DTA bit. Set DMABCRH [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the number of transfers in ETCRA. [4] Set each bit in DMACRA and DMACRB.
H8S/2215 Group Section 7 DMA Controller (DMAC) 7.4.6 Block Transfer Mode In block transfer mode, transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in DMACRA to 1. In block transfer mode, a transfer of the specified block size is carried out in response to a single transfer request, and this is executed the specified number of times.
H8S/2215 Group Section 7 DMA Controller (DMAC) Figure 7.11 illustrates operation in block transfer mode when MARB is designated as a block area.
H8S/2215 Group Section 7 DMA Controller (DMAC) Figure 7.12 illustrates operation in block transfer mode when MARA is designated as a block area.
H8S/2215 Group Section 7 DMA Controller (DMAC) ETCRB is decremented by 1 every block transfer, and when the count reaches H'0000 the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this point, an interrupt request is sent to the CPU or DTC. Figure 7.13 shows the operation flow in block transfer mode.
H8S/2215 Group Section 7 DMA Controller (DMAC) Transfer requests (activation sources) consist of A/D conversion end interrupt, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 2 compare match/input capture A interrupts. For details, see section 7.3.4, DMA Control Register (DMACR). Figure 7.14 shows an example of the setting procedure for block transfer mode. [1] Set each bit in DMABCRH. Block transfer mode setting · Set the FAE bit to 1 to select full address mode.
H8S/2215 Group 7.4.7 Section 7 DMA Controller (DMAC) DMAC Activation Sources DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The activation sources that can be specified depend on the transfer mode, as shown in table 7.8. Table 7.
Section 7 DMA Controller (DMAC) H8S/2215 Group When DTE = 0, such as after completion of a transfer, a request from the selected activation source is not sent to the DMAC, regardless of the DTA bit. In this case, the relevant interrupt request is sent to the CPU or DTC. In case of overlap with a CPU interrupt source or DTC activation source (DTA = 0), the interrupt request flag is not cleared by the DMAC. Activation by USB Request: A USB request (DREQ signal) may be specified as the activation source.
H8S/2215 Group 7.4.8 Section 7 DMA Controller (DMAC) Basic DMAC Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 7.15. In this example, wordsize transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations.
H8S/2215 Group Section 7 DMA Controller (DMAC) 7.4.9 DMAC Bus Cycles (Dual Address Mode) Short Address Mode: Figure 7.16 shows a transfer example in which TEND* output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space.
H8S/2215 Group Section 7 DMA Controller (DMAC) Full Address Mode (Cycle Steal Mode): Figure 7.17 shows a transfer example in which TEND*output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space.
H8S/2215 Group Section 7 DMA Controller (DMAC) Full Address Mode (Burst Mode): Figure 7.18 shows a transfer example in which TEND* output is enabled and word-size full address mode transfer (burst mode) is performed from external 16- bit, 2-state access space to external 16-bit, 2-state access space.
H8S/2215 Group Section 7 DMA Controller (DMAC) Full Address Mode (Block Transfer Mode): Figure 7.19 shows a transfer example in which TEND* output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.
H8S/2215 Group Section 7 DMA Controller (DMAC) DREQ Signal Level Activation Timing (Normal Mode): Set the DTA bit for the channel for which the DREQ signal is selected to 1. Figure 7.20 shows an example of DREQ level activated normal mode transfer.
H8S/2215 Group 7.4.10 Section 7 DMA Controller (DMAC) DMAC Multi-Channel Operation The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table 7.9 summarizes the priority order for DMAC channels. Table 7.
H8S/2215 Group Section 7 DMA Controller (DMAC) 7.4.11 Relation between the DMAC, External Bus Requests, and the DTC There can be no break between a DMA cycle read and a DMA cycle write. This means that a refresh cycle, external bus release cycle, or DTC cycle is not generated between the external read and external write in a DMA cycle.
H8S/2215 Group Section 7 DMA Controller (DMAC) Resumption of transfer on interrupted channel DTE = 1 DTME = 0 [1] Check that DTE = 1 and DTME = 0 in DMABCRL. [2] Write 1 to the DTME bit. [1] No Yes Set DTME bit to 1 [2] Transfer ends Transfer continues Figure 7.22 Example of Procedure for Continuing Transfer on Channel Interrupted by NMI Interrupt 7.4.
H8S/2215 Group Section 7 DMA Controller (DMAC) 7.4.14 Clearing Full Address Mode Figure 7.24 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure.
H8S/2215 Group 7.5 Section 7 DMA Controller (DMAC) Interrupts The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.10 shows the interrupt sources and their priority order. Table 7.
H8S/2215 Group Section 7 DMA Controller (DMAC) 7.6 Usage Notes 7.6.1 DMAC Register Access during Operation Except for forced termination, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, the DMAC register should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below. 1.
H8S/2215 Group Section 7 DMA Controller (DMAC) 2. If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC register is read as shown in figure 7.27. DMA transfer cycle CPU longword read MAR upper word read MAR lower word read DMA read DMA write φ DMA internal address DMA control DMA register operation Note: Idle [1] Transfer source Transfer destination Read Write Idle [2] The lower word of MAR is the updated value after the operation in [1]. Figure 7.
Section 7 DMA Controller (DMAC) 7.6.4 H8S/2215 Group Activation Source Acceptance At the start of activation source acceptance, a low level is detected in both DREQ signal falling edge sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that occurs before execution of the DMABCRL write to enable transfer.
H8S/2215 Group Section 8 Data Transfer Controller (DTC) Section 8 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 8.
H8S/2215 Group Section 8 Data Transfer Controller (DTC) Internal address bus CPU interrupt request Legend: MRA, MRB: CRA, CRB: SAR: DAR: DTCERA to DTCERF: DTVECR: Register information MRA MRB CRA CRB DAR SAR DTC service request DTVECR Interrupt request DTCERA to DTCERF On-chip RAM DTC Control logic Interrupt controller Internal data bus DTC mode registers A and B DTC transfer count registers A and B DTC source address register DTC destination address register DTC enable registers A to F DTC ve
H8S/2215 Group 8.2 Section 8 Data Transfer Controller (DTC) Register Descriptions DTC has the following registers. • DTC mode register A (MRA) • DTC mode register B (MRB) • DTC source address register (SAR) • DTC destination address register (DAR) • DTC transfer count register A (CRA) • DTC transfer count register B (CRB) These six registers cannot be directly accessed from the CPU.
H8S/2215 Group Section 8 Data Transfer Controller (DTC) 8.2.1 DTC Mode Register A (MRA) MRA selects the DTC operating mode. Bit Bit Name Initial Value R/W Description 7 SM1 Undefined — Source Address Mode 1 and 0 6 SM0 Undefined — These bits specify an SAR operation after a data transfer.
H8S/2215 Group 8.2.2 Section 8 Data Transfer Controller (DTC) DTC Mode Register B (MRB) MRB selects the DTC operating mode. Bit Bit Name Initial Value R/W Description 7 CHNE — DTC Chain Transfer Enable Undefined This bit specifies a chain transfer. For details, refer to section 8.5.4, Chain Transfer. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER, are not performed.
H8S/2215 Group Section 8 Data Transfer Controller (DTC) 8.2.5 DTC Transfer Count Register A (CRA) CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
H8S/2215 Group 8.2.8 Section 8 Data Transfer Controller (DTC) DTC Vector Register (DTVECR) DTVECR enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. Bit Bit Name Initial Value R/W 7 SWDTE R/W* DTC Software Activation Enable 0 Description This bit specifies whether DTC software startup is enabled or prohibited. 0: Prohibits DTC software startup. 1: Enables DTC software startup.
Section 8 Data Transfer Controller (DTC) 8.3 H8S/2215 Group Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. DTCER is used to select the activation interrupt source. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared. Table 8.
H8S/2215 Group Section 8 Data Transfer Controller (DTC) Source flag cleared Clear controller Clear DTCER On-chip supporting module IRQ interrupt DTVECR Interrupt request Selection circuit Select Clear request DTC CPU Interrupt controller Interrupt mask Figure 8.2 Block Diagram of DTC Activation Source Control 8.4 Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'FFEBC0 to H'FFEFBF).
H8S/2215 Group Section 8 Data Transfer Controller (DTC) Lower address 0 Register information start address 1 2 MRA SAR MRB DAR Register information CRB CRA Chain transfer 3 MRA SAR MRB DAR Register information for 2nd transfer in chain transfer CRB CRA 4 bytes Figure 8.3 Correspondence between DTC Vector Address and Register Information DTC vector address Register information start address Register information Chain transfer Figure 8.
H8S/2215 Group Table 8.
H8S/2215 Group Section 8 Data Transfer Controller (DTC) 8.5 Operation Register information is stored in an on-chip RAM. When activated, the DTC reads register information in an on-chip RAM and transfers data. After the data transfer, it writes updated register information back to the memory. Pre-storage of register information in the memory makes it possible to transfer data over any required number of channels. The transfer mode can be specified as normal, repeat, and block transfer mode.
H8S/2215 Group Section 8 Data Transfer Controller (DTC) Table 8.3 summarizes DTC functions. Table 8.3 Overview of DTC Functions Address Register Transfer Mode Activation Source Source Destination Normal mode • • • • 24 bits 24 bits • One byte or one word data is transferred in response to a single transfer request. • The memory address is incremented by 1 or 2. • The number of times of data transfer is designated as 1 to 65,536.
H8S/2215 Group Section 8 Data Transfer Controller (DTC) 8.5.1 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 8.4 shows the register information in normal mode, and figure 8.6 shows the memory mapping in normal mode. Table 8.
H8S/2215 Group 8.5.2 Section 8 Data Transfer Controller (DTC) Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 8.
H8S/2215 Group Section 8 Data Transfer Controller (DTC) 8.5.3 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed.
H8S/2215 Group 8.5.4 Section 8 Data Transfer Controller (DTC) Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set respectively. Figure 8.9 shows the memory map for chain transfer.
H8S/2215 Group Section 8 Data Transfer Controller (DTC) 8.5.5 Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control.
H8S/2215 Group Section 8 Data Transfer Controller (DTC) φ DTC activation request DTC request Data transfer Vector read Read Write Read Write Address Transfer information read Transfer information write Figure 8.
H8S/2215 Group Section 8 Data Transfer Controller (DTC) Table 8.7 DTC Execution Status Vector Read Register information Read/Write Data read Data Write Internal Operations Mode I J K L M Normal 1 6 1 1 3 Repeat 1 6 1 1 3 Block transfer 1 6 N N 3 Legend: N: Block size (initial setting of CRAH and CRAL) Table 8.
H8S/2215 Group 8.6 Procedures for Using DTC 8.6.1 Activation by Interrupt Section 8 Data Transfer Controller (DTC) The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the enable bits for the interrupt sources to be used as the activation sources to 1.
H8S/2215 Group Section 8 Data Transfer Controller (DTC) 8.7 Examples of Use of the DTC 8.7.1 Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0).
H8S/2215 Group Section 8 Data Transfer Controller (DTC) 4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. 5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. 6.
Section 8 Data Transfer Controller (DTC) Page 228 of 846 H8S/2215 Group REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 9 I/O Ports Section 9 I/O Ports Table 9.1 summarizes the port functions. The pins of each port also have other functions such as input/output or external interrupt input pins of on-chip peripheral modules. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only ports do not have a DR and a DDR.
H8S/2215 Group Section 9 I/O Ports Table 9.
H8S/2215 Group Table 9.
H8S/2215 Group Section 9 I/O Ports Table 9.
H8S/2215 Group 9.1 Section 9 I/O Ports Port 1 Port 1 is an 8-bit I/O port. The port 1 has the following registers. • Port 1 data direction register (P1DDR) • Port 1 data register (P1DR) • Port 1 register (PORT1) 9.1.1 Port 1 Data Direction Register (P1DDR) P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. Since this is a write-only register, bit manipulation instructions should not be used to write to it. For details, see section 2.9.
H8S/2215 Group Section 9 I/O Ports 9.1.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit Bit Name Initial Value R/W Description 7 P17DR 0 R/W 6 P16DR 0 R/W An output data for a pin is stored when the pin function is specified to a general purpose output port. 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W 9.1.3 Port 1 Register (PORT1) PORT1 shows the pin states.
H8S/2215 Group 9.1.4 Section 9 I/O Ports Pin Functions Port 1 pins also function as TPU I/O pins, external interrupt input pins (IRQ1, IRQ0), external USB transceiver input, and address bus (A23 to A20) output pins. The correspondence between the register specification and the pin functions is shown below. Table 9.
H8S/2215 Group Section 9 I/O Ports Table 9.4 P15 Pin Function FADSEL in UCTLR* 3 1 TPU Channel 1 Setting* Output P15DDR Pin function 0 1 Input or Initial Value — — 0 1 — TIOCB1 output P15 input P15 output FSE0 output* 3 TIOCB1 input TCLKC input Table 9.5 P14 Pin Function TPU Channel 1 Setting* 1 Output P14DDR Pin function Input or Initial Value — 0 1 TIOCA1 output P14 input P14 output TIOCA1 input 2 * IRQ0 input Notes: 1.
H8S/2215 Group Table 9.7 AE3 to AE0* Section 9 I/O Ports P12 Pin Function 1 Other than B'1111 3 FADSEL in UCTLR* 0 2 TPU Channel 0 Setting* Output P12DDR — Pin function TIOCC0 output Input or Initial Value 0 P12 input B'1111 1 — — — 1 — P12 output RCV input* — 3 A22 output TIOCC0 input TCLKA input Table 9.8 AE3 to AE0* P11 Pin Function 1 Other than (B'1110 to B'1111) 3 FADSEL in UCTLR* 0 2 TPU Channel 0 Setting* Output P11DDR — Pin function TIOCB0 output Table 9.
H8S/2215 Group Section 9 I/O Ports 9.2 Port 3 Port 3 is a 7-bit I/O port also functioning as SCI I/O and external interrupt input (IRQ4, IRQ5). • Port 3 data direction register (P3DDR) • Port 3 data register (P3DR) • Port 3 register (PORT3) • Port 3 open-drain control register (P3ODR) 9.2.1 Port 3 Data Direction Register (P3DDR) The individual bits of P3DDR specify input or output for the pins of port 3.
H8S/2215 Group 9.2.2 Section 9 I/O Ports Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins (P36 to P30). Bit Bit Name Initial Value R/W Description 7 — — Reserved Undefined This bit is undefined and cannot be modified. 6 P36DR 0 R/W 5 P35DR 0 R/W 4 P34DR 0 R/W 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 P30DR 0 R/W 9.2.3 An output data for a pin is stored when the pin function is specified to a general purpose output port.
H8S/2215 Group Section 9 I/O Ports 9.2.4 Port 3 Open-Drain Control Register (P3ODR) P3ODR controls the PMOS on/off status for each port 3 pin (P36 to P30). Bit Bit Name Initial Value R/W Description 7 — — Reserved Undefined This bit is undefined and cannot be modified. 6 P36ODR 0 R/W 5 P35ODR 0 R/W 4 P34ODR 0 R/W 3 P33ODR 0 R/W 2 P32ODR 0 R/W 1 P31ODR 0 R/W 0 P30ODR 0 R/W 9.2.
H8S/2215 Group Section 9 I/O Ports Table 9.11 P35 Pin Function CKE1 in SCR_1 0 C/A in SMR_1 1 0 CKE0 in SCR_1 0 P35DDR 0 Pin function 1 P35 input 1 — 1 — — — — — P35 output* SCK1 output* SCK1 output* SCK1 input 1 IRQ5 input* 2 2 2 Notes: 1. When used as an external interrupt pin, do not use for another function. 2.
H8S/2215 Group Section 9 I/O Ports Table 9.14 P32 Pin Function CKE1 in SCR_0 0 C/A in SMR_0 0 CKE0 in SCR_0 Pin function * 1 — 1 — — — — — 0 P32DDR Note: 1 0 1 P32 input P32 output SCK0 output SCK0 output IRQ4 input* SCK0 input When used as an external interrupt pin, do not use for another function. Table 9.15 P31 Pin Function RE in SCR_0 0 P31DDR Pin function 1 0 1 — P31 input P31 output RxD0 input Table 9.
H8S/2215 Group 9.3 Section 9 I/O Ports Port 4 Port 4 is a 4-bit I/O port also functioning as A/D converter analog input. Port 4 has the following register. • Port 4 register (PORT4) 9.3.1 Port 4 Register (PORT4) PORT4 shows port 4 pin states. PORT4 cannot be modified. Bit Bit Name Initial Value R/W Description 7 to 4 — Undefined — Reserved 3 P43 R 2 P41 —* —* 1 P41 R 0 P40 —* —* Note: 9.3.2 These bits are undefined.
H8S/2215 Group Section 9 I/O Ports 9.4 Port 7 Port 7 is a 5-bit I/O port also functioning as bus control output, manual reset input, and 8-bit timer I/O. Port 7 has the following registers. • Port 7 data direction register (P7DDR) • Port 7 data register (P7DR) • Port 7 register (PORT7) 9.4.1 Port 7 Data Direction Register (P7DDR) P7DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 7.
H8S/2215 Group 9.4.2 Section 9 I/O Ports Port 7 Data Register (P7DR) P7DR stores output data for the port 7 pins. Bit Bit Name Initial Value R/W Description 7 to 5 — — Reserved 4 P74DR 0 R/W 3 P73DR 0 R/W 2 P72DR 0 R/W 1 P71DR 0 R/W 0 P70DR 0 R/W Undefined These bits are undefined and cannot be modified. 9.4.3 Stores output data for the port 7 pins. Port 7 Register (PORT7) PORT7 shows the pin states.
H8S/2215 Group Section 9 I/O Ports 9.4.4 Pin Functions Port 7 pins also function as bus control output pins, manual reset input pin, and 8 bit timer input/output. Port 7 pin functions are shown below. Table 9.17 P74 Pin Function MRESE 0 P74DDR Pin function 1 0 1 — P74 input P74 output MRES input Table 9.
H8S/2215 Group Section 9 I/O Ports Table 9.21 P70 Pin Function Operating Mode Modes 4 to 6 P70DDR Pin function Mode 7 0 1 0 1 P70 input CS4 output P70 input P70 output TMRI01, TMCI01 input 9.5 Port 9 Port 9 pins also function as A/D converter analog input and D/A converter analog output pins. The port 9 has the following register. • Port 9 register (PORT9) 9.5.1 Port 9 Register (PORT9) PORT9 shows port 9 pin states.
H8S/2215 Group Section 9 I/O Ports 9.6 Port A Port A is a 4-bit I/O port that also functions as address bus (A19 to A16) output, external USB transceiver output, and SCI_2 I/O, and interrupt input. The port A has the following registers. • Port A data direction register (PADDR) • Port A data register (PADR) • Port A register (PORTA) • Port A pull-up MOS control register (PAPCR) • Port A open-drain control register (PAODR) 9.6.
H8S/2215 Group 9.6.2 Section 9 I/O Ports Port A Data Register (PADR) PADR stores output data for the port A pins. Bit Bit Name Initial Value R/W Description 7 to 4 — — Reserved 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 PA0DR 0 R/W Undefined These bits are undefined and cannot be modified. 9.6.3 An output data for a pin is stored when the pin function is specified to a general purpose output port. Port A Register (PORTA) PORTA shows port A pin states.
H8S/2215 Group Section 9 I/O Ports 9.6.4 Port A MOS Pull-Up Control Register (PAPCR) PAPCR controls the function of the port A input pull-up MOS. PAPCR is valid for port input and SCI input pins. Bit Bit Name Initial Value R/W Description 7 to 4 — — Reserved 3 PA3PCR* 0 R/W 2 PA2PCR 0 R/W 1 PA1PCR 0 R/W 0 PA0PCR 0 R/W Note: Undefined These bits are undefined and cannot be modified. * 9.6.
H8S/2215 Group 9.6.6 Section 9 I/O Ports Pin Functions Port A pins also function as address bus (A19 to A16) output, external USB transceiver output, SCI_2 I/O, and interrupt input. The correspondence between the register specification and the pin functions is shown below. Table 9.
H8S/2215 Group Section 9 I/O Ports Table 9.23 PA2 Pin Function Operating mode AE3 to AE0 Modes 4 to 6 1011 or 11xx Mode 7 Other than 1011 or 11xx RE in SCR_2 — PA2DDR — 0 1 — 0 1 — A18 output PA2 input PA2 output RxD2 input PA2 input PA2 output RxD2 input Pin function 0 — 1 0 1 Table 9.
H8S/2215 Group 9.6.7 Section 9 I/O Ports Port A Input Pull-Up MOS Function Port A has a built-in input pull-up MOS function that can be controlled by software. Input pull-up MOS can be specified as on or off for individual bits. Table 9.26 summarizes the input pull-up MOS states. Table 9.
H8S/2215 Group Section 9 I/O Ports 9.7.1 Port B Data Direction Register (PBDDR) The individual bits of PBDDR specify input or output for the pins of port B. Since this is a writeonly register, bit manipulation instructions should not be used to write to it. For details, see section 2.9.4, Accessing Registers Containing Write-Only Bits.
H8S/2215 Group 9.7.3 Section 9 I/O Ports Port B Register (PORTB) PORTB shows port B pin states. Bit Bit Name Initial Value R/W Description 7 PB7 —* R PB6 —* R 5 PB5 —* R If the port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B read is performed while PBDDR bits are cleared to 0, the pin states are read. 6 4 PB4 —* R 3 PB3 —* R 2 PB2 —* R 1 PB1 R 0 PB0 —* —* Note: 9.7.4 R Determined by the status of pins PB7 to PB0.
H8S/2215 Group Section 9 I/O Ports 9.7.5 Pin Functions Port B pins also function as address bus (A15 to A9) output pins. The correspondence between the register specification and the pin functions is shown below. Table 9.27 PB7 Pin Function Operating mode AE3 to AE0 PB7DDR Pin function Modes 4 to 6 B'1xxx Mode 7 Other than B'1xxx — — 0 1 0 1 A15 output PB7 input PB7 output PB7 input PB7 output Table 9.
H8S/2215 Group Section 9 I/O Ports Table 9.31 PB3 Pin Function Operating mode AE3 to AE0 Modes 4 to 6 Other than B'00xx PB3DDR Pin function Mode 7 B'00xx — — 0 1 0 1 A11 output PB3 input PB3 output PB3 input PB3 output Table 9.32 PB2 Pin Function Operating mode AE3 to AE0 Modes 4 to 6 Other than B'0010 or B'000x PB2DDR Pin function Mode 7 B'0010 or B'000x — — 0 1 0 1 A10 output PB2 input PB2 output PB2 input PB2 output Table 9.
H8S/2215 Group Section 9 I/O Ports 9.7.6 Port B Input Pull-Up MOS Function Port B has a built-in input pull-up MOS function that can be controlled by software. Input pull-up MOS can be specified as on or off for individual bits. Table 9.35 summarizes the input pull-up MOS states. Table 9.
H8S/2215 Group 9.8.1 Section 9 I/O Ports Port C Data Direction Register (PCDDR) The individual bits of PCDDR specify input or output for the pins of port C. Since this is a writeonly register, bit manipulation instructions should not be used to write to it. For details, see section 2.9.4, Accessing Registers Containing Write-Only Bits. Bit Bit Name Initial Value R/W Description 7 PC7DDR 0 W 6 PC6DDR 0 W Modes 4 and 5 Port C pins are address outputs regardless of the PCDDR settings.
H8S/2215 Group Section 9 I/O Ports 9.8.3 Port C Register (PORTC) PORTC shows port C pin states. Bit Bit Name Initial Value R/W Description 7 PC7 —* R PC6 —* R 5 PC5 —* R If a port C read is performed while PCDDR bits are set to 1, the PCDR values are read. If a port C read is performed while PCDDR bits are cleared to 0, the pin states are read. 6 4 PC4 —* R 3 PC3 —* R 2 PC2 —* R 1 PC1 R 0 PC0 —* —* Note: 9.8.4 * R Determined by the states of pins PC7 to PC0.
H8S/2215 Group 9.8.5 Section 9 I/O Ports Pin Functions Port C pins also function as Address bus (A7 to A0) output. The correspondence between the register specification and the pin functions is shown below. Table 9.36 PC7 Pin Function Operating Mode PC7DDR Pin Function Mode 6* Modes 4 and 5 Mode 7 — 0 1 0 1 A7 output PC7 input A7 output PC7 input PC7 output Table 9.
H8S/2215 Group Section 9 I/O Ports Table 9.41 PC2 Pin Function Operating Mode PC2DDR Pin Function Mode 6* Modes 4 and 5 Mode 7 — 0 1 0 1 A2 output PC2 input A2 output PC2 input PC2 output Table 9.42 PC1 Pin Function Operating Mode PC1DDR Pin Function Mode 6* Modes 4 and 5 Mode 7 — 0 1 0 1 A1 output PC1 input A1 output PC1 input PC1 output Table 9.
H8S/2215 Group 9.8.6 Section 9 I/O Ports Port C Input Pull-Up MOS Function Port C has a built-in input pull-up MOS function that can be controlled by software. Input pull-up MOS can be used in modes 6 and 7, and can be specified as on or off for individual bits. Table 9.44 summarizes the input pull-up MOS states. Table 9.
H8S/2215 Group Section 9 I/O Ports 9.9.1 Port D Data Direction Register (PDDDR) The individual bits of PDDDR specify input or output for the pins of port D. Since this is a writeonly register, bit manipulation instructions should not be used to write to it. For details, see section 2.9.4, Accessing Registers Containing Write-Only Bits. Bit Bit Name Initial Value R/W Description 7 PD7DDR 0 W 6 PD6DDR 0 W Modes 4 to 6 Port D pins automatically function as data input/output pins.
H8S/2215 Group 9.9.3 Section 9 I/O Ports Port D Register (PORTD) PORTD shows port D pin states. Bit Bit Name Initial Value R/W Description 7 PD7 —* R PD6 —* R 5 PD5 —* R If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D read is performed while PDDDR bits are cleared to 0, the pin states are read. 6 4 PD4 —* R 3 PD3 —* R 2 PD2 —* R 1 PD1 R 0 PD0 —* —* Note: 9.9.4 R Determined by the states of pins PD7 to PD0.
H8S/2215 Group Section 9 I/O Ports 9.9.5 Pin Functions Port D pins also functions as data bus (D15 to D8) I/O. The correspondence between the register specification and the pin functions in shown below. Table 9.45 PD7 Pin Function Operating Mode PD7DDR Pin Function Modes 4 to 6 Mode 7 — 0 1 D15 input/output PD7 input PD7 output Table 9.46 PD6 Pin Function Operating Mode PD6DDR Pin Function Modes 4 to 6 Mode 7 — 0 1 D14 input/output PD6 input PD6 output Table 9.
H8S/2215 Group Section 9 I/O Ports Table 9.50 PD2 Pin Function Operating Mode Modes 4 to 6 PD2DDR Pin Function Mode 7 — 0 1 D10 input/output PD2 input PD2 output Table 9.51 PD1 Pin Function Operating Mode Modes 4 to 6 PD1DDR Pin Function Mode 7 — 0 1 D9 input/output PD1 input PD1 output Table 9.52 PD0 Pin Function Operating Mode Modes 4 to 6 PD0DDR Pin Function 9.9.
H8S/2215 Group Section 9 I/O Ports 9.10 Port E Port E is an 8-bit I/O port that also has data bus (D7 to D0) I/O. The port E has the following registers. • Port E data direction register (PEDDR) • Port E data register (PEDR) • Port E register (PORTE) • Port E Pull-up MOS control register (PEPCR) 9.10.1 Port E Data Direction Register (PEDDR) The individual bits of PEDDR specify input or output for the pins of port E.
H8S/2215 Group 9.10.2 Section 9 I/O Ports Port E Data Register (PEDR) PEDR stores output data for the port E pins. Bit Bit Name Initial Value R/W Description 7 PE7DR 0 R/W 6 PE6DR 0 R/W An output data for a pin is stored when the pin function is specified to a general purpose output port. 5 PE5DR 0 R/W 4 PE4DR 0 R/W 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W 0 PE0DR 0 R/W 9.10.3 Port E Register (PORTE) PORTE shows port E pin states.
H8S/2215 Group Section 9 I/O Ports 9.10.4 Port E Pull-Up MOS Control Register (PEPCR) PEPCR controls on/off states of the input pull-up MOS of port E. Bit Bit Name Initial Value R/W Description 7 PE7PCR 0 R/W 6 PE6PCR 0 R/W When the pin is in the input state, the input pull-up MOS of the input pin is on when the corresponding bit is set to 1. 5 PE5PCR 0 R/W 4 PE4PCR 0 R/W 3 PE3PCR 0 R/W 2 PE2PCR 0 R/W 1 PE1PCR 0 R/W 0 PE1PCR 0 R/W 9.10.
H8S/2215 Group Section 9 I/O Ports Table 9.56 PE5 Pin Function Operating Mode Modes 4 to 6 Mode 7 Bus Mode 8-bit bus mode PE5DDR 0 1 — 0 1 PE5 input PE5 output D5 input/output PE5 input PE5 output Pin Function 16-bit bus mode — Table 9.57 PE4 Pin Function Operating Mode Modes 4 to 6 Mode 7 Bus Mode 8-bit bus mode PE4DDR 0 1 — 0 1 PE4 input PE4 output D4 input/output PE4 input PE4 output Pin Function 16-bit bus mode — Table 9.
H8S/2215 Group Section 9 I/O Ports Table 9.60 PE1 Pin Function Operating Mode Modes 4 to 6 Mode 7 Bus Mode 8-bit bus mode PE1DDR 0 1 — 0 1 PE1 input PE1 output D1 input/output PE1 input PE1 output Pin Function 16-bit bus mode — Table 9.61 PE0 Pin Function Operating Mode Modes 4 to 6 Mode 7 Bus Mode 8-bit bus mode PE0DDR 0 1 — 0 1 PE0 input PE0 output D0 input/output PE0 input PE0 output Pin Function Page 272 of 846 16-bit bus mode — REJ09B0140-0900 Rev. 9.
H8S/2215 Group 9.10.6 Section 9 I/O Ports Port E Input Pull-Up MOS State Port E has a built-in input pull-up MOS function that can be controlled by software. Input pull-up MOS can be used in 8-bit bus mode in modes 4 to 6 or in mode 7, and can be specified as on or off for individual bits. Table 9.62 summarizes the input pull-up MOS states. Table 9.
H8S/2215 Group Section 9 I/O Ports 9.11 Port F Port F is an 8-bit I/O port that also has external interrupt input (IRQ2, IRQ3), bus control sign I/O, system clock output. The port F has the following registers. • Port F data direction register (PFDDR) • Port F data register (PFDR) • Port F register (PORTF) 9.11.1 Port F Data Direction Register (PFDDR) The individual bits of PFDDR specify input or output for the pins of port F.
H8S/2215 Group 9.11.2 Section 9 I/O Ports Port F Data Register (PFDR) PFDR stores output data for the port F pins. Bit Bit Name Initial Value R/W Description 7 PF7DR 0 R/W 6 PF6DR 0 R/W An output data for a pin is stored when the pin function is specified to a general purpose output port. 5 PF5DR 0 R/W 4 PF4DR 0 R/W 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W 0 PF0DR 0 R/W 9.11.3 Port F Register (PORTF) PORTF shows port F pin states.
H8S/2215 Group Section 9 I/O Ports 9.11.4 Pin Functions Port F is an 8-bit I/O port. Port F pins also function as external interrupt input (IRQ2 and IRQ3), bus control signal, and system clock output (φ). Table 9.63 PF7 Pin Function PF7DDR Pin function 0 1 PF7 input φ output Table 9.64 PF6 Pin Function Operating Mode Modes 4 to 6 PF6DDR Pin function Mode 7 — 0 1 AS output PF6 input PF6 output Table 9.
H8S/2215 Group Section 9 I/O Ports Table 9.67 PF3 Pin Function Operating Mode Modes 4 to 6 Mode 7 Bus Mode 16 bits PF3DDR — 0 1 0 LWR output PF3 input PF3 output PF3 input Pin function 8 bits — ADTRG input * 2 IRQ3 input * 1 PF3 output 1 Notes: 1. ADTRG input when TRGS0=TRGS1=1. 2. When used as an external interrupt input pin, do not use as an I/O pin for another function. Table 9.
H8S/2215 Group Section 9 I/O Ports 9.12 Port G Port G is a 5-bit I/O port that also has functioning as external interrupt input (IRQ7) and bus control output (CS0 to CS3). The port G has the following registers. • Port G data direction register (PGDDR) • Port G data register (PGDR) • Port G register (PORTG) 9.12.1 Port G Data Direction Register (PGDDR) The individual bits of PGDDR specify input or output for the pins of port G. If port G is, an undefined value will be read.
H8S/2215 Group 9.12.2 Section 9 I/O Ports Port G Data Register (PGDR) PGDR stores output data for the port G pins. Bit Bit Name Initial Value R/W Description 7 to 5 — — Reserved 4 PG4DR 0 R/W 3 PG3DR 0 R/W 2 PG2DR 0 R/W 1 PG1DR 0 R/W 0 PG0DR 0 R/W Undefined These bits are undefined and cannot be modified. 9.12.3 An output data for a pin is stored when the pin function is specified to a general purpose output port. Port G Register (PORTG) PORTG shows port G pin states.
H8S/2215 Group Section 9 I/O Ports 9.12.4 Pin Functions Port G is an 8-bit I/O port. Port G pins also function as external interrupt inputs (IRQ7) and bus control signals (CS0 to CS3). Table 9.71 PG4 Pin Function Operating Mode Modes 4 to 6 PG4DDR Pin function Mode 7 0 1 0 1 PG4 input CS0 output PG4 input PG4 output Table 9.72 PG3 Pin Function Operating Mode Modes 4 to 6 PG3DDR Pin function Mode 7 0 1 0 1 PG3 input CS1 output PG3 input PG3 output Table 9.
H8S/2215 Group 9.13 Section 9 I/O Ports Handling of Unused Pins Unused input pins should be fixed high or low. Generally, the input pins of CMOS products are high-impedance. Leaving unused pins open can cause the generation of intermediate levels due to peripheral noise induction. This can result in shoot-through current inside the device and cause it to malfunction. Table 9.76 lists examples of ways to handle unused pins. For the handling of dedicated boundary scan pins that are unused, see section 14.
Section 9 I/O Ports Page 282 of 846 H8S/2215 Group REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Section 10 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises three 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 10.1 and figure 10.1, respectively. 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Legend: TSTR: Timer start register TSYR: Timer synchro register TCR: Timer control register TMDR: Timer mode register A/D converter convertion start signal TGRC TGRD TGRB TGRB TGRB TCNT TCNT TGRA TCNT TGRA Module data bus TSR TSR TGRA Bus interface Internal data bus TSTR TIER TIER TIER TSR TIOR TIOR TIORH TIORL Common Control logic TMDR Channel 2 TCR TMDR Channel 1 TIOR (H, L): TIER: TSR: TGR (A, B, C, D): TCR SCK0 (to SCI0) TM
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Item Channel 0 DTC activation TGR compare match or TGR compare match or TGR compare match input capture input capture or input capture DMAC activation TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture A/D converter trigger TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture 5 sources 4 sources 4 sources • • •
H8S/2215 Group 10.2 Section 10 16-Bit Timer Pulse Unit (TPU) Input/Output Pins Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3 H8S/2215 Group Register Descriptions The TPU has the following registers.
H8S/2215 Group 10.3.1 Section 10 16-Bit Timer Pulse Unit (TPU) Timer Control Register (TCR) The TCR registers control the TCNT operation for each channel. The TPU has a total of three TCR registers, one for each channel (channels 0 to 2). TCR register settings should be made only when TCNT operation is stopped. Bit Bit Name Initial value R/W Description 7 CCLR2 0 R/W Counter Clear 2 to 0 6 CCLR1 0 R/W 5 CCLR0 0 R/W These bits select the TCNTcounter clearing source. See tables 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.5 TPSC2 to TPSC0 (channel 0) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description 0 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: counts on TCLKC pin input 1 External clock: counts on TCLKD pin input 1 1 0 1 Table 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
H8S/2215 Group 10.3.2 Section 10 16-Bit Timer Pulse Unit (TPU) Timer Mode Register (TMDR) The TMDR registers are used to set the operating mode for each channel. The TPU has three TMDR registers, one for each channel. TMDR register settings should be made only when TCNT operation is stopped. Bit Bit Name Initial value R/W 7, — — All 1 6 5 Description Reserved These bits are always read as 1 and cannot be modified.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.8 MD3 to MD0 Bit 3 Bit2 Bit 1 Bit 0 1 MD3* 2 MD2* MD1 MD0 Description 0 0 0 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 × — 1 1 0 1 1 × × Legend: ×: Don’t care Notes: 1. MD3 is reserved bit. In a write, it should be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3.
H8S/2215 Group 10.3.3 Section 10 16-Bit Timer Pulse Unit (TPU) Timer I/O Control Register (TIOR) The TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for channel 0, and one each for channels 1 and 2. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0).
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.4 Timer Interrupt Enable Register (TIER) The TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has three TIER registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TTGE R/W A/D Conversion Start Request Enable 0 Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W Description 1 TGIEB R/W TGR Interrupt Enable B 0 Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB disabled 1: Interrupt requests (TGIB) by TGFB enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.5 Timer Status Register (TSR) The TSR registers indicate the status of each channel. The TPU has three TSR registers, one for each channel. Bit Bit Name Initial value R/W 7 TCFD 1 R Description Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1 and 2. In channel 0, bit 7 is reserved. It is always read as 0 and cannot be modified.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W 3 TGFD 0 R/(W)* Description Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channel 0. The write value should always be 0 to clear this flag. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W 1 TGFB 0 R/(W)* Description Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. The write value should always be 0 to clear this flag.
H8S/2215 Group 10.3.6 Section 10 16-Bit Timer Pulse Unit (TPU) Timer Counter (TCNT) The TCNT registers are 16-bit counters. The TPU has three TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 10.3.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.9 Timer Synchro Register (TSYR) TSYR selects independent operation or synchronous operation for the channel 0 to 2 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Bit Name Initial Value R/W 7 to 3 — — 2 SYNC2 0 R/W Timer Synchro 2 to 0 1 SYNC1 0 R/W 0 SYNC0 0 R/W These bits select whether operation is independent of or synchronized with other channels.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) 10.4 Interface to Bus Master 10.4.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read from or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 10.2.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Internal data bus H Bus master L Module data bus Bus interface TCR Figure 10.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)] Internal data bus H Bus master L Module data bus Bus interface TMDR Figure 10.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)] Internal data bus H Bus master L Module data bus Bus interface TCR TMDR Figure 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) 10.5 Operation 10.5.1 Basic Functions Each channel has a TCNT and TGR. TCNT performs up-counting, and is also capable of freerunning operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Counter Operation: When one of bits CST0 to CST2 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting.
Section 10 16-Bit Timer Pulse Unit (TPU) H8S/2215 Group 2. Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Counter cleared by TGR compare match TCNT value TGR H'0000 Time CST bit Flag cleared by software or DTC activation TGF Figure 10.8 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. 1. Example of setting procedure for waveform output by compare match Figure 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) 2. Examples of waveform output operation Figure 10.10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. 1. Example of input capture operation setting procedure Figure 10.12 shows an example of the input capture operation setting procedure.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) 2. Example of input capture operation Figure 10.13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
H8S/2215 Group 10.5.2 Section 10 16-Bit Timer Pulse Unit (TPU) Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 2 can all be designated for synchronous operation.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation: Figure 10.15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing sources. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) • When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 10.16. Compare match signal Timer general register Buffer register Comparator TCNT Figure 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Examples of Buffer Operation 1. When TGR is an output compare register Figure 10.19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) 2. When TGR is an input capture register Figure 10.20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) 10.5.4 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0 % to 100 % duty. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Example of PWM Mode Setting Procedure: Figure 10.21 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] Select counter clearing source [2] Select waveform output level [3] Set TGR [4] Set PWM mode [5] Start count [6] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.23 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs as the duty.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.24 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) 10.5.5 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. 1. Phase counting mode 1 Figure 10.26 shows an example of phase counting mode 1 operation, and table 10.20 summarizes the TCNT up/down-count conditions.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) 2. Phase counting mode 2 Figure 10.27 shows an example of phase counting mode 2 operation, and table 10.21 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 10.27 Example of Phase Counting Mode 2 Operation Table 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) 3. Phase counting mode 3 Figure 10.28 shows an example of phase counting mode 3 operation, and table 10.22 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 10.28 Example of Phase Counting Mode 3 Operation Table 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) 4. Phase counting mode 4 Figure 10.29 shows an example of phase counting mode 4 operation, and table 10.23 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 10.29 Example of Phase Counting Mode 4 Operation Table 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) 10.6 Interrupts 10.6.1 Interrupt Source and Priority There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1.
Section 10 16-Bit Timer Pulse Unit (TPU) H8S/2215 Group Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 8 input capture/compare match interrupts, four each for channel 0, and two each for channels 1 and 2.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) 10.7 Operation Timing 10.7.1 Input/Output Timing TCNT Count Timing: Figure 10.30 shows TCNT count timing in internal clock operation, and figure 10.31 shows TCNT count timing in external clock operation. φ Internal clock Falling edge Rising edge TCNT input clock N-1 TCNT N N+1 N+2 Figure 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture: Figure 10.34 shows the timing when counter clearing by compare match occurrence is specified, and figure 10.35 shows the timing when counter clearing by input capture occurrence is specified. φ Compare match signal Counter clear signal TCNT N TGR N H'0000 Figure 10.34 Counter Clear Timing (Compare Match) φ Input capture signal Counter clear signal N TCNT H'0000 N TGR Figure 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing: Figures 10.36 and 10.37 show the timing in buffer operation. φ TCNT n n+1 Compare match signal TGRA, TGRB n TGRC, TGRD N N Figure 10.36 Buffer Operation Timing (Compare Match) φ Input capture signal TCNT N TGRA, TGRB n TGRC, TGRD N+1 N N+1 n N Figure 10.37 Buffer Operation Timing (Input Capture) Page 338 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group 10.7.2 Section 10 16-Bit Timer Pulse Unit (TPU) Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 10.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. φ TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 10.38 TGI Interrupt Timing (Compare Match) TGF Flag Setting Timing in Case of Input Capture: Figure 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) TCFV Flag/TCFU Flag Setting Timing: Figure 10.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 10.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing. φ TCNT input clock TCNT (overflow) H'FFFF H'0000 Overflow signal TCFV flag TCIV interrupt Figure 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 10.42 shows the timing for status flag clearing by the CPU, and figure 10.43 shows the timing for status flag clearing by the DTC or DMAC. TSR write cycle T1 T2 φ Address TSR address Write signal Status flag Interrupt request signal Figure 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) 10.8 Usage Notes Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10.45 shows the timing in this case. TCNT write cycle T2 T1 φ TCNT address Address Write signal Counter clear signal TCNT N H'0000 Figure 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Contention between TGR Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 10.47 shows the timing in this case. TGR write cycle T2 T1 φ TGR address Address Write signal Compare match signal Prohibited TCNT N N+1 TGR N M TGR write data Figure 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 10.48 shows the timing in this case. TGR write cycle T2 T1 φ Buffer register address Address Write signal Compare match signal Buffer register write data Buffer register N M N TGR Figure 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Contention between TGR Write and Input Capture: If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10.50 shows the timing in this case. TGR write cycle T2 T1 φ Address TGR address Write signal Input capture signal TCNT TGR M M Figure 10.50 Contention between TGR Write and Input Capture Page 346 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10.51 shows the timing in this case. Buffer register write cycle T2 T1 φ Buffer register address Address Write signal Input capture signal TCNT N M TGR Buffer register N M Figure 10.
H8S/2215 Group Section 10 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Overflow/Underflow: If there is an up-count or downcount in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 10.53 shows the operation timing when there is contention between TCNT write and overflow.
H8S/2215 Group Section 11 8-Bit Timers (TMR) Section 11 8-Bit Timers (TMR) This LIS includes an 8-bit timer module with two channels. Each channel has an 8-bit counter and two registers that are constantly compared with the TCNT value to detect compare match events. The 8-bit timer module can thus be used for a variety of functions, including pulse output with an arbitrary duty cycle. 11.1 Features The features of the 8-bit timer module are listed below.
H8S/2215 Group Section 11 8-Bit Timers (TMR) External clock source TMCI01 Internal clock sources φ/8 φ/64 φ/8192 Clock select Clock 1 Clock 0 TCORA_0 TCORA_1 Compare match A1 Compare match A0 Comparator A_0 Overflow 1 Overflow 0 TMO0 TMRI01 TCNT_0 Comparator A_1 TCNT_1 Clear 0 TMO1 Control logic Compare match B1 Compare match B0 Comparator B_0 A/D conversion start request signal Internal bus Clear 1 Comparator B_1 TCORB_0 TCORB_1 TCSR_0 TCSR_1 TCR_0 TCR_1 CMIA0 CMIB0 OVI0 CMIA1 CMIB
H8S/2215 Group 11.2 Section 11 8-Bit Timers (TMR) Input/Output Pins Table 11.1 summarizes the input and output pins of the TMR. Table 11.1 Pin Configuration Channel Name Symbol I/O Function 0 Timer output pin 0 TMO0 Output Outputs at compare match 1 Timer output pin 1 TMO1 Output Outputs at compare match All Timer clock input pin 01 TMCI01 Input Inputs external clock for counter Timer reset input pin 01 TMRI01 Input Inputs external reset to counter 11.
Section 11 8-Bit Timers (TMR) 11.3.2 H8S/2215 Group Time Constant Registers A (TCORA) The TCORA_0 and TCORA_1 registers are 8-bit readable/writable registers. TCORA_0 and TCORA_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. The value in TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding CMFA flag in TCSR is set to 1. Note, however, that comparison is disabled during the T2 state of a TCOR write cycle.
H8S/2215 Group 11.3.4 Section 11 8-Bit Timers (TMR) Time Control Registers (TCR) The TCR registers select the clock source and the time at which TCNT is cleared, and enable interrupts. Bit Bit Name Initial Value R/W Description 7 CMIEB 0 R/W Compare Match Interrupt Enable B Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set to 1.
H8S/2215 Group Section 11 8-Bit Timers (TMR) Table 11.2 Clock Input to TCNT and Count Condition TCR Bit 2 Bit 1 Bit 0 Channel CKS2 CKS1 CKS0 Description TMR_0 0 0 1 TMR_1 All Note: 11.3.
H8S/2215 Group Section 11 8-Bit Timers (TMR) Bit Bit Name Initial Value R/W 7 CMFB 0 R/(W)* Compare Match Flag B 0 [Setting condition] • Set when TCNT matches TCORB [Clearing conditions] • Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB • When DTC is activated by CMIB interrupt, while DISEL bit is 0, and transfer counter value is not 0 R/(W)* Compare Match Flag A 0 [Setting condition] • Set when TCNT matches TCORA [Clearing conditions] • Cleared by reading CMFA when CMFA = 1, then
H8S/2215 Group Section 11 8-Bit Timers (TMR) Bit Bit Name Initial Value R/W Description 1 0 OS1 OS0 0 0 R/W R/W Output Select 1 and 0 These bits select a method of TMO pin output when compare match A of TCOR and TCNT occurs. 00: No change when compare match A occurs 01: 0 is output when compare match A occurs 10: 1 is output when compare match A occurs 11: Output is inverted when compare match A occurs (toggle output) Note: The write value should always be 0 to clear these flags. * 11.
H8S/2215 Group Section 11 8-Bit Timers (TMR) 11.5 Operation Timing 11.5.1 TCNT Incrementation Timing Figure 11.3 shows the count timing for internal clock input. Figure 11.4 shows the count timing for external clock signal. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The counter will not increment correctly if the pulse width is less than these values.
H8S/2215 Group Section 11 8-Bit Timers (TMR) 11.5.2 Setting of Compare Match Flags CMFA and CMFB The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare match signal is not generated until the next incrementation clock input. Figure 11.5 shows this timing.
H8S/2215 Group 11.5.4 Section 11 8-Bit Timers (TMR) Timing of Compare Match Clear The timer counter is cleared when compare match A or B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 11.7 shows the timing of this operation. φ Compare match signal TCNT N H'00 Figure 11.7 Timing of Compare Match Clear 11.5.5 Timing of TCNT External Reset TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR.
H8S/2215 Group Section 11 8-Bit Timers (TMR) 11.5.6 Timing of Overflow Flag (OVF) Setting The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 11.9 shows the timing of this operation. φ TCNT H'FF H'00 Overflow signal OVF Figure 11.9 Timing of OVF Setting Page 360 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group 11.6 Section 11 8-Bit Timers (TMR) Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match count mode). In this case, the timer operates as below. 11.6.
H8S/2215 Group Section 11 8-Bit Timers (TMR) 11.7 Interrupts 11.7.1 Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 11.3. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts. Table 11.
H8S/2215 Group 11.7.2 Section 11 8-Bit Timers (TMR) A/D Converter Activation The A/D converter can be activated only by TMR_0 compare match A. If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurrence of TMR_0 compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. 11.8 Usage Notes 11.8.
H8S/2215 Group Section 11 8-Bit Timers (TMR) 11.8.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 11.11 shows this operation. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 11.11 Contention between TCNT Write and Increment Page 364 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group 11.8.3 Section 11 8-Bit Timers (TMR) Contention between TCOR Write and Compare Match During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match signal is prohibited even if a compare match event occurs. Figure 11.12 shows this operation. TCOR write cycle by CPU T1 T2 φ Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare match signal Prohibited Figure 11.
H8S/2215 Group Section 11 8-Bit Timers (TMR) 11.8.4 Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 11.4. Table 11.4 Timer Output Priorities Output Setting Priority Toggle output High 1 output 0 output No change 11.8.
H8S/2215 Group Section 11 8-Bit Timers (TMR) Table 11.5 Switching of Internal Clock and TCNT Operation No.
H8S/2215 Group Section 11 8-Bit Timers (TMR) No. 4 Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from high to high Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite Notes: 1. 2. 3. 4. 11.8.6 Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented.
H8S/2215 Group Section 12 Watchdog Timer (WDT) Section 12 Watchdog Timer (WDT) The watchdog timer (WDT) is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows.
H8S/2215 Group Section 12 Watchdog Timer (WDT) 12.2 Register Descriptions The WDT has the following three registers. For details, refer to section 23, List of Registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to by a different method to normal registers. For details, refer to section 12.5.1, Notes on Register Access. • Timer counter (TCNT) • Timer control/status register (TCSR) • Reset control/status register (RSTCSR) 12.2.
H8S/2215 Group Section 12 Watchdog Timer (WDT) Bit Bit Name Initial Value R/W Description 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4, 3 — All 1 — Reserved These bits are always read as 1 and cannot be modified.
H8S/2215 Group Section 12 Watchdog Timer (WDT) 12.2.3 Reset Control/Status Register (RSTCSR) RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, and not by the WDT internal reset signal caused by overflows.
H8S/2215 Group Section 12 Watchdog Timer (WDT) 12.3 Operation 12.3.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1. TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. When the RSTE bit of the RSTCSR is set to 1, and if the TCNT overflows, an internal reset signal for this LSI is issued.
H8S/2215 Group Section 12 Watchdog Timer (WDT) 12.3.2 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) With WDT0, the WOVF bit in RSTCSR is set to 1 if TCNT overflows in watchdog timer mode. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire chip. This timing is illustrated in figure 12.3. φ TCNT H'FF H'00 Overflow signal (internal signal) WOVF Internal reset signal 518 states (WDT0) Figure 12.
H8S/2215 Group 12.3.3 Section 12 Watchdog Timer (WDT) Interval Timer Mode To use the WDT as an interval timer, clear bit WT/IT in TCSR to 0 and set bit TME to 1. When the interval timer is operating, an interval timer interrupt (WOVI) is generated each time the TCNT overflows. Therefore, an interrupt can be generated at intervals. TCNT count Overflow H'FF Overflow Overflow Overflow Time H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI Legend: WOVI: Interval interrupt request generation Figure 12.
H8S/2215 Group Section 12 Watchdog Timer (WDT) 12.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. Table 12.1 WDT Interrupt Source Name Interrupt Source Interrupt Flag DTC Activation WOVI TCNT overflow WOVF Impossible 12.5 Usage Notes 12.5.
H8S/2215 Group Section 12 Watchdog Timer (WDT) Writing to RSTCSR: RSTCSR must be written to by a word transfer to address H'FF76. It cannot be written to with byte instructions. Figure 12.7 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF bit differs from that for writing to the RSTE and RSTS bits. To write 0 to the WOVF bit, the upper byte of the written word must contain H'A5 and the lower byte must contain H'00.
H8S/2215 Group Section 12 Watchdog Timer (WDT) 12.5.2 Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 12.8 shows this operation. TCNT write cycle T1 T2 φ Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.8 Contention between TCNT Write and Increment 12.5.
H8S/2215 Group 12.5.5 Section 12 Watchdog Timer (WDT) Internal Reset in Watchdog Timer Mode This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation, however TCNT and TCSR of the WDT are reset. TCNT, TCSR, or RSTCR cannot be written to for 132 states following an overflow. During this period, any attempt to read the WOVF flag is not acknowledged. Accordingly, wait 132 states after overflow to write 0 to the WOVF flag for clearing. 12.5.
Section 12 Watchdog Timer (WDT) Page 380 of 846 H8S/2215 Group REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 13 Serial Communication Interface Section 13 Serial Communication Interface This LSI has three independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA).
H8S/2215 Group Section 13 Serial Communication Interface • Average transfer rate generator (SCI_0): In H8S/2215 720 kbps, 460.784 kbps, or 115.196 kbps can be selected at 16 MHz. In H8S/2215R, H8S/2215T and H8S/2215C 921.569 kbps, 720 kbps, 460.784 kbps, or 115.196 kbps can be selected at 16 MHz. 921.053 kbps, 720 kbps, 460.526 kbps, or 115.132 kbps can be selected at 24 MHz.
H8S/2215 Group 13.1.1 Section 13 Serial Communication Interface Block Diagram Bus interface Module data bus SCMR TDR RDR Internal data bus Figure 13.1 shows the block diagram of the SCI_0 for H8S/2215, figure 13.2 shows the block diagram of the SCI_0 for H8S/2215R, H8S/2215T and H8S/2215C. Figure 13.2 shows the block diagram of the SCI_1 and SCI_2.
Bus interface Module data bus RDR RxD0 TDR RSR TxD0 PG1/IRQ7 Parity generation Parity check BRR SCMR SSR SCR SMR SEMRA_0 SEMRB_0 control transmission and reception TSR Internal data bus H8S/2215 Group Section 13 Serial Communication Interface φ Baud rate generator φ/4 φ/16 φ/64 Clock TEI TXI RXI ERI C/A CKE1 SSE Average transfer rate generator External clock SCK0 SCI transfer clock generator in TPU 10.667 MHz · 115.152 kbps · 460.606 kbps 16 MHz · 115.196 kbps · 460.
H8S/2215 Group Module data bus RDR TDR SCMR BRR SSR φ SCR RxD RSR TSR Baud rate generator SMR Detecting parity φ/4 φ/16 control transmission and reception TxD Internal data bus Bus interface Section 13 Serial Communication Interface φ/64 Clock Parity check External clock SCK Legend: RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register SCMR: Sma
H8S/2215 Group Section 13 Serial Communication Interface 13.2 Input/Output Pins Table 13.1 shows the serial pins for each SCI channel. Table 13.1 Pin Configuration Channel Pin Name* I/O Function 0 SCK0 I/O SCI_0 clock input/output 1 2 Note: 13.
H8S/2215 Group Section 13 Serial Communication Interface • Serial extended mode register B_0 (SEMRB_0) (only for channel 0 in H8S/2215R, H8S/2215T and H8S/2215C) • Bit rate register (BRR) 13.3.1 Receive Shift Register (RSR) RSR is a shift register that is used to receive serial data input to the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 13.3.
H8S/2215 Group Section 13 Serial Communication Interface 13.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bits in SMR have different functions in normal mode and smart card interface mode.
H8S/2215 Group Section 13 Serial Communication Interface Bit Bit Name Initial Value R/W Description 2 MP R/W Multiprocessor Mode (enabled only in asynchronous mode) 0 When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. For details, see section 13.5, Multiprocessor Communication Function.
H8S/2215 Group Section 13 Serial Communication Interface • Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Bit Name Initial Value R/W Description 7 GM 0 R/W GSM Mode Setting this bit to 1 allows GSM mode operation. In GSM mode, the TEND set timing is put forward to 11.0 etu from the start and the clock output control function is appended. For details, see section 13.7.9, Clock Output Control. 0: Normal smart card interface mode operation (initial value) (1) The TEND flag is generated 12.
H8S/2215 Group Section 13 Serial Communication Interface Bit Bit Name Initial Value R/W Description 5 PE R/W Parity Enable 0 When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. Set this bit to 1 in smart card interface mode. 4 O/E 0 R/W Parity Mode (valid only when the PE bit is 1) 0: Selects even parity 1: Selects odd parity For details on the usage of this bit in smart card interface mode, see section 13.7.
H8S/2215 Group Section 13 Serial Communication Interface 13.3.6 Serial Control Register (SCR) SCR is a register that enables or disables SCI transfer operations and interrupt requests, and is also used to selection of the transfer clock source. For details on interrupt requests, refer to section 13.9, Interrupts. Some bits in SCR have different functions in normal mode and smart card interface mode.
H8S/2215 Group Section 13 Serial Communication Interface Bit Bit Name Initial Value R/W Description 3 MPIE R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) 0 When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed.
H8S/2215 Group Section 13 Serial Communication Interface • Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Bit Name Initial Value R/W Description 7 TIE R/W Transmit Interrupt Enable 0 When this bit is set to 1, TXI interrupt request is enabled. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0, or clearing the TIE bit to 0.
H8S/2215 Group Section 13 Serial Communication Interface Bit Bit Name Initial Value R/W Description 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) Write 0 to this bit in Smart Card interface mode. When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RERF, FER, and ORER flags in SSR, are not performed.
H8S/2215 Group Section 13 Serial Communication Interface 13.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bits in SSR have different functions in normal mode and smart card interface mode.
H8S/2215 Group Bit 5 Section 13 Serial Communication Interface Bit Name Initial Value R/W ORER R/(W)* Overrun Error 0 Description 1 [Setting condition] • When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either.
H8S/2215 Group Section 13 Serial Communication Interface Bit 3 Bit Name Initial Value R/W PER R/(W)* Parity Error 0 Description 1 [Setting condition] • When a parity error is detected during reception If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either.
H8S/2215 Group Section 13 Serial Communication Interface • Smart Card Interface Mode (When SMIF in SCMR is 1) Bit 7 Bit Name Initial Value R/W TDRE 1 Description R/(W)* Transmit Data Register Empty 1 Indicates whether TDR contains transmit data.
H8S/2215 Group Section 13 Serial Communication Interface Bit 5 Bit Name Initial Value R/W ORER 0 Description R/(W)* Overrun Error 1 Indicates that an overrun error occurred during reception, causing abnormal termination. [Setting condition] • When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial cannot be continued while the ORER flag is set to 1.
H8S/2215 Group Section 13 Serial Communication Interface Bit Bit Name Initial Value R/W Description 2 TEND Transmit End 1 R This bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to TDR. [Setting conditions] • • When the TE bit in SCR is 0 and the ERS bit is also 0 When the ESR bit is 0 and the TDRE bit is 1 after the specified interval following transmission of 1-byte data.
H8S/2215 Group Section 13 Serial Communication Interface 13.3.8 Smart Card Mode Register (SCMR) SCMR selects the operation in smart card interface or the data Transfer formats. Bit Bit Name Initial Value R/W Description 7 to 4 — All 1 — Reserved 3 0 R/W Smart Card Data Transfer Direction These bits are always read as 1. DIR Selects the serial/parallel conversion format. 0: LSB-first in transfer 1: MSB-first in transfer The bit setting is valid only when the transfer data format is 8 bits.
H8S/2215 Group 13.3.9 Section 13 Serial Communication Interface Serial Extended Mode Register (SEMR) (Only for Channel 0 in H8S/2215) SEMR extends the functions of SCI_0. SEMR0 enables selection of the SCI_0 select function in synchronous mode, base clock setting in asynchronous mode, and also clock source selection and automatic transfer rate setting. Figure 13.3 shows an example of the internal base clock when an average transfer rate is selected and figure 13.
H8S/2215 Group Section 13 Serial Communication Interface Bit Bit Name Initial Value R/W Description 2 ACS2 0 R/W Asynchronous Clock Source Select 2 to 0 1 ACS1 0 0 ACS0 0 R/W These bits select the clock source in asynchronous mode. R/W When an average transfer rate is selected, the base clock is set automatically regardless of the ABCS value. Note that average transfer rates are not supported for operating frequencies other than 10.667 MHz and 16 MHz.
Sep 16, 2010 REJ09B0140-0900 Rev. 9.00 1 1 2 2 3 3 4 5 7 8 9 10 11 12 Base clock 1 1 2 2 3 3 4 5 7 8 9 10 11 12 1 1 2 2 4 5 6 7 5.76 MHz 4 5 8 MHz 6 8 3 4 5 6 7 8 13 14 15 16 1 2 3 4 5 6 7 8 7 1 2 3 4 Average transfer rate = 5.76 MHz/8 = 720 kbps Average error = ±0% 8 5 6 7 8 1 2 3 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 1 bit = base clock × 8* 3 3 Note: * As the base clock synchronization varies, so does the length of one bit.
Page 406 of 846 6 7 8 9 1 bit = base clock × 16* 1.8421 MHz 2 3 4 5 10 11 Average transfer rate =1.8421 MHz/16 = 115.132 kbps Average error with 115.2 kbps = -0.0059% 1 3 MHz 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 1 2 6 7 8 9 1 bit = base clock × 16* 7.3684 MHz 2 3 4 5 1 5 6 1 bit = base clock × 8* 5.76 MHz 3 4 7 Average transfer rate = 5.
REJ09B0140-0900 Rev. 9.00 Sep 16, 2010 1 1 1 4 4 7.3846 MHz 3 4 8 MHz 3 3 5 5 5 6 6 6 7 7 7 8 8 8 Average transfer rate = 7.3846 MHz/8 = 923.077 kbps Average error relative to 921.6 kbps = +0.16% 1 bit = 8 base clocks* 2 2 2 1 9 9 Note: * As the base clock synchronization varies, so does the length of one bit. Internal base clock = 8 MHz x 12/13 = 7.
Page 408 of 846 SCK0 Base clock = 9.6 MHz × 15/16 = 9 MHz (Average) Clock enable TIOCA1 output Base clock (TIOCA0 + TIOCC0) output = 9.6 MHz TIOCC0 output = 4.8 MHz TIOCA0 output = 4.8 MHz 5 5 9.6 MHz 4 4 6 6 6 7 7 7 8 8 8 1 bit = Base clock × 16* 9 MHz 3 4 5 3 3 9 9 9 10 11 12 13 14 15 10 11 12 13 14 15 10 11 12 13 14 15 16 Average transfer rate = 9 MHz/16 = 562.5 kbps 2 2 2 16 1 1 Note: * The length of one bit varies according to the base clock synchronization.
REJ09B0140-0900 Rev. 9.00 Sep 16, 2010 SCK0 Base clock = 6 MHz × 23/25 = 5.52 MHz (Average) 25 1 1 1 2 4 5 5 5 6 6 6 7 7 7 8 8 8 9 9 9 10 11 12 10 11 12 10 11 12 13 Average transfer rate = 5.52 MHz/16 = 345 kbps 1 bit = Base clock × 16* 4 6 MHz 3 4 5.52 MHz 2 3 2 3 13 13 18 14 15 16 1 2 18 19 20 14 15 16 17 14 15 16 17 Note: * The length of one bit varies according to the base clock synchronization.
Page 410 of 846 SCK0 Base clock = 9.6 MHz × 23/25 = 8.832 MHz (Average) Clock enable (TIOCA1×TIOCA2) output TIOCA2 output TIOCA1 output Base clock (TIOCA0 + TIOCC0) output = 9.6 MHz TIOCC0 output = 4.8 MHz TIOCA0 output = 4.8 MHz 5 5 6 6 8.832 MHz 4 5 6 9.6 MHz 4 4 7 7 7 8 8 8 1 bit = Base clock × 16* 3 3 3 9 9 9 10 11 12 10 11 12 13 13 14 15 14 15 16 1 2 3 4 5 6 7 16 17 18 19 20 21 22 23 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Average transfer rate = 8.
H8S/2215 Group Section 13 Serial Communication Interface 13.3.10 Serial Extended Mode Register A_0 (SEMRA_0) (Only for Channel 0 in H8S/2215R, H8S/2215T and H8S/2215C) SEMRA_0 extends the functions of SCI_0. SEMR0 enables selection of the SCI_0 select function in synchronous mode, base clock setting in asynchronous mode, and also clock source selection and automatic transfer rate setting. Figure 13.4 shows an example of the internal base clock when an average transfer rate is selected and figure 13.
H8S/2215 Group Section 13 Serial Communication Interface Bit Bit Name Initial Value R/W Description 3 ABCS 0 R/W Asynchronous Base Clock Select Selects the 1-bit-interval base clock in asynchronous mode. The ABCS setting is valid in asynchronous mode (C/A = 0 in SMR).
H8S/2215 Group Section 13 Serial Communication Interface Bit Bit Name Initial Value R/W Description 2 ACS2 0 1 ACS1 0 0 ACS0 0 R/W 0101: 115.196 kbps average transfer rate (for φ = 16 MHz only) is selected (SCI_0 operates on base clock with R/W frequency of 16 times transfer rate) R/W 0110: 460.
H8S/2215 Group Section 13 Serial Communication Interface Bit Bit Name Initial Value R/W Description 7 ACS3 R/W Asynchronous Clock Source Select 0 Selects the clock source in asynchronous mode depending on the combination with the ACS2 to ACS0 (bits 2 to 0 in SEMRA_0). For details, see section 13.3.9, Serial Extended Mode Register (SEMR) (Only for channel 0 in H8S/2215). 6 to 4 — Undefined 3 TIOCA2E 1 — Reserved The write value should always be 0.
H8S/2215 Group Section 13 Serial Communication Interface 13.3.12 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 13.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode, clocked synchronous mode, and Smart Card interface mode.
H8S/2215 Group Section 13 Serial Communication Interface a 1-bit transfer interval) can be selected. For details, see section 13.7.5, Receive Data Sampling Timing and Reception Margin. Tables 13.5 and 13.7 show the maximum bit rates with external clock input. When the ABCS bit in SCI_0's serial extended mode register (SEMR) is set to 1 in asynchronous mode, the maximum bit rates are twice those shown in table 13.3. Table 13.
H8S/2215 Group Section 13 Serial Communication Interface Operating Frequency φ (MHz) 3.6864 4 4.9152 5 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.
H8S/2215 Group Section 13 Serial Communication Interface Operating Frequency φ (MHz) 9.8304 10 12 12.288 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 174 –0.26 2 177 –0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.
H8S/2215 Group Section 13 Serial Communication Interface Operating Frequency φ (MHz) 17.2032 Bit Rate (bps) n N 18 Error (%) n N 19.6608 Error (%) n N 20 Error (%) n N Error (%) 110 3 75 0.48 3 79 –0.12 3 86 0.31 3 88 –0.25 150 2 223 0.00 2 233 0.16 2 255 0.00 3 64 0.16 300 2 111 0.00 2 116 0.16 2 127 0.00 2 129 0.16 600 1 223 0.00 1 233 0.16 1 255 0.00 2 64 0.16 1200 1 111 0.00 1 116 0.16 1 127 0.00 1 129 0.16 2400 0 223 0.
H8S/2215 Group Section 13 Serial Communication Interface Table 13.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) Maximum Bit Rate (kbps) Maximum Bit Rate (kbps) φ (MHz) ABCS = 0 ABCS = 1 n N φ (MHz) ABCS = 0 ABCS = 1 n N 2 62.5 125.0 0 0 9.8304 307.2 614.4 0 0 2.097152 65.536 131.027 0 0 10 312.5 625.0 0 0 2.4576 76.8 153.6 0 0 12 375.0 750.0 0 0 3 93.75 187.5 0 0 12.288 384.0 768.0 0 0 3.6864 115.2 230.4 0 0 14 437.5 875.0 0 0 4 125.
H8S/2215 Group Section 13 Serial Communication Interface Table 13.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) Bit Rate 2 4 6 8 10 16 (bps) n N n N n N n N n N n N 110 3 70 — — 250 2 124 2 249 3 124 — — 3 249 500 1 249 2 124 2 249 — — 3 124 1k 1 124 1 249 2 124 — — 2 249 2.
H8S/2215 Group Section 13 Serial Communication Interface Table 13.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, when n = 0 and S = 372) Operating Frequency φ (MHz) 5.00 Bit Rate (bps) N Error (%) 6720 0 0.01 9600 0 30.00 7.00 7.1424 10.00 10.7136 13.00 Error (%) N Error (%) N Error (%) N Error (%) 1 30.00 1 28.57 1 0.01 1 7.14 2 13.33 0 1.99 0 0.00 1 30.00 1 25.00 1 8.99 N N Error (%) Operating Frequency φ (MHz) 14.2848 16.00 18.00 20.
H8S/2215 Group 13.4 Section 13 Serial Communication Interface Operation in Asynchronous Mode Figure 13.6 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line.
H8S/2215 Group Section 13 Serial Communication Interface 13.4.1 Data Transfer Format Table 13.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, refer to section 13.5, Multiprocessor Communication Function. Table 13.
H8S/2215 Group 13.4.2 Section 13 Serial Communication Interface Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in Figure 13.7.
H8S/2215 Group Section 13 Serial Communication Interface 16 clocks * 8 clocks * 0 7 15 0 7 15 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Note: * Figure 13.7 shows an example when the ABCS bit of SEMR is cleared to 0. When ABCS is set to 1, the clock frequency of basic clock is 8 times the bit rate and the receive data is sampled at the rising edge of the 4th pulse of the basic clock. Figure 13.
H8S/2215 Group 13.4.4 Section 13 Serial Communication Interface SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 13.9. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1.
H8S/2215 Group Section 13 Serial Communication Interface 13.4.5 Data Transmission (Asynchronous Mode) Figure 13.10 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
H8S/2215 Group Section 13 Serial Communication Interface Figure 13.11 shows a sample flowchart for transmission in asynchronous mode. [1] Initialization [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
H8S/2215 Group Section 13 Serial Communication Interface 13.4.6 Serial Data Reception (Asynchronous Mode) Figure 13.12 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line. If a start bit is detected, the SCI performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
H8S/2215 Group Section 13 Serial Communication Interface Table 13.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 13.13 shows a sample flow chart for serial data reception. Table 13.
H8S/2215 Group Section 13 Serial Communication Interface [1] Initialization [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing and break detection: If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1.
H8S/2215 Group Section 13 Serial Communication Interface [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? Yes No Framing error processing No Clear RE bit in SCR to 0 PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 13.13 Sample Serial Reception Data Flowchart (2) REJ09B0140-0900 Rev. 9.
Section 13 Serial Communication Interface 13.5 H8S/2215 Group Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code.
H8S/2215 Group Section 13 Serial Communication Interface Transmitting station Serial transmission line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) Legend: MPB: Multiprocessor bit ID transmission cycle = receiving station specification (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID Figure 13.
H8S/2215 Group Section 13 Serial Communication Interface [1] Initialization [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0.
H8S/2215 Group 13.5.2 Section 13 Serial Communication Interface Multiprocessor Serial Data Reception Figure 13.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 13.
H8S/2215 Group Section 13 Serial Communication Interface Initialization Start reception Read MPIE bit in SCR [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID.
H8S/2215 Group Section 13 Serial Communication Interface [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 13.17 Sample Multiprocessor Serial Reception Flowchart (2) REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 13 Serial Communication Interface 13.6 Operation in Clocked Synchronous Mode Figure 13.18 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next.
H8S/2215 Group 13.6.2 Section 13 Serial Communication Interface SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, the TE and RE bits in SCR should be cleared to 0, then the SCI should be initialized as described in a sample flowchart in figure 13.19. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
H8S/2215 Group Section 13 Serial Communication Interface 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. Continuous transmission is possible because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has been completed. 3.
H8S/2215 Group Section 13 Serial Communication Interface Initialization [1] Start transmission Read TDRE flag in SSR SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
H8S/2215 Group Section 13 Serial Communication Interface 13.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 13.22 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization synchronous with a synchronous clock input or output, starts receiving data, and stores the received data in RSR. 2.
H8S/2215 Group Section 13 Serial Communication Interface Initialization [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1.
H8S/2215 Group Section 13 Serial Communication Interface Initialization [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
H8S/2215 Group 13.7 Section 13 Serial Communication Interface Operation in Smart Card Interface The SCI supports an IC card (Smart Card) interface that conforms to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface mode is carried out by means of a register setting. 13.7.1 Pin Connection Example Figure 13.25 shows an example of connection with the Smart Card.
H8S/2215 Group Section 13 Serial Communication Interface 13.7.2 Data Format (Except for Block Transfer Mode) Figure 13.26 shows the transfer data format in Smart Card interface mode. • One frame consists of 8-bit data plus a parity bit in asynchronous mode. • In transmission, a guard time of at least 2 etu (Elementary time unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame.
H8S/2215 Group Section 13 Serial Communication Interface bits in SCMR to 0. According to Smart Card regulations, clear the O/E bit in SMR to 0 to select even parity mode. (Z) A Z Z A A A A A A Z Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp (Z) State Figure 13.28 Inverse Convention (SDIR = SINV = O/E = 1) With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order.
H8S/2215 Group Section 13 Serial Communication Interface 13.7.5 Receive Data Sampling Timing and Reception Margin In Smart Card interface mode an internal clock generated by the on-chip baud rate generator can only be used as a transmission/reception clock. In this mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (fixed to 16 times in normal asynchronous mode) as determined by bits BCP1 and BCP0.
H8S/2215 Group 13.7.6 Section 13 Serial Communication Interface Initialization Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. Clear the TE and RE bits in SCR to 0. 2. Clear the error flags ERS, PER, and ORER in SSR to 0. 3. Set the GM, BLK, O/E, BCP0, BCP1, CKS0, CKS1 bits in SMR. Set the PE bit to 1. 4. Set the SMIF, SDIR, and SINV bits in SCMR.
Section 13 Serial Communication Interface 13.7.7 H8S/2215 Group Serial Data Transmission (Except for Block Transfer Mode) As data transmission in Smart Card interface mode involves error signal sampling and retransmission processing, the operations are different from those in normal serial communication interface mode (except for block transfer mode). Figure 13.30 illustrates the retransfer operation when the SCI is in transmit mode. 1.
H8S/2215 Group Section 13 Serial Communication Interface nth transfer frame Transfer frame n + 1 Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 TDRE Transfer to TSR from TDR Transfer to TSR from TDR Transfer to TSR from TDR TEND FER/ERS Figure 13.30 Retransfer Operation in SCI Transmit Mode The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag set timing is shown in figure 13.31.
H8S/2215 Group Section 13 Serial Communication Interface Start Initialization Start transmission ERS = 0? No Yes Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted ? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0 End Figure 13.32 Example of Transmission Processing Flow Page 454 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group 13.7.8 Section 13 Serial Communication Interface Serial Data Reception (Except for Block Transfer Mode) Data reception in Smart Card interface mode uses the same operation procedure as for normal serial communication interface mode. Figure 13.33 illustrates the retransfer operation when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1.
H8S/2215 Group Section 13 Serial Communication Interface nth transfer frame Transfer frame n + 1 Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 RDRF PER Figure 13.33 Retransfer Operation in SCI Receive Mode Start Initialization Start reception ORER = 0 and PER = 0 No Yes Error processing No RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 13.
H8S/2215 Group 13.7.9 Section 13 Serial Communication Interface Clock Output Control When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE0 and CKE1 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 13.35 shows the timing for fixing the clock output level. In this example, GM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled. CKE0 SCK Specified pulse width Specified pulse width Figure 13.
H8S/2215 Group Section 13 Serial Communication Interface When returning to smart card interface mode from software standby mode 1. Exit the software standby state. 2. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the normal duty. Normal operation Software standby Normal operation Figure 13.36 Clock Halt and Restart Procedure Page 458 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group 13.8 Section 13 Serial Communication Interface SCI Select Function The SCI_0 supports the SCI select function which allows clock synchronous communication between master LSI and one of multiple slave LSI. Figure 13.37 shows an example of communication using the SCI select function. Figure 13.38 shows the operation. The master LSI can communicate with slave LSI_A by bringing SEL_A and SEL_B signals low and high, respectively.
H8S/2215 Group Section 13 Serial Communication Interface Communication between master LSI Communication between master LSI and slave LSI_A and slave LSI_B Period of M_SCK = high [Master LSI] M_SCK M_TxD D0 D1 D7 D0 D1 D7 M_RxD D0 D1 D7 D0 D1 D7 SEL_A SEL_B [Slave LSI_A] IRQ7_A (SEL_A) SCK0_A Fixed high level RSR0_A TxD0_A D0 Hi-Z D0 D6 D1 D7 Hi-Z D7 [Slave LSI_B] IRQ7_B (SEL_B) Fixed high level SCK0_B RSR0_B TxD0_B D0 Hi-Z D0 D6 D1 D7 D7 Hi-Z Figure 13.
H8S/2215 Group Section 13 Serial Communication Interface 13.9 Interrupts 13.9.1 Interrupts in Normal Serial Communication Interface Mode Table 13.12 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated.
H8S/2215 Group Section 13 Serial Communication Interface Table 13.
H8S/2215 Group 13.9.2 Section 13 Serial Communication Interface Interrupts in Smart Card Interface Mode Table 13.13 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt (TEI) request cannot be used in this mode. Note: In case of block transfer mode, see section 13.9.1, Interrupts in Normal Serial Communication Interface Mode. Table 13.
Section 13 Serial Communication Interface 13.10 H8S/2215 Group Usage Notes 13.10.1 Break Detection and Processing (Asynchronous Mode Only) When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and possibly the PER flag. Note that as the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 13.10.
H8S/2215 Group Section 13 Serial Communication Interface In particular, data transmission cannot be completed correctly unless the TDRE flag is cleared using the CPU. SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When operating on an external clock, set t>4 clocks. Figure 13.39 Example of Clocked Synchronous Transmission by DMAC or DTC 13.10.
H8S/2215 Group Section 13 Serial Communication Interface No All data transmitted? [1] Yes Read TEND flag in SSR No TEND = 1 Yes [1] Data being transmitted is interrupted. After exiting software standby mode, etc., normal CPU transmission is possible by setting TE to 1, reading SSR, writing TDR, and clearing TDRE to 0, but note that if the DTC* or the DMAC has been activated, the remaining data in DTCRAM will be transmitted when TE and TIE are set to 1. [2] Includes module stop mode.
H8S/2215 Group Section 13 Serial Communication Interface Start of transmission End of transmission Exit from software standby Transition to software standby TE bit SCK output pin Port input/output TxD output pin Port input/output Final TxD bit retention High output Port SCI TxD output Port input/output Port High output* SCI TxD output Note: * Initialized by the software standby. Figure 13.
H8S/2215 Group Section 13 Serial Communication Interface Read RDRF flag in SSR RDRF = 1 No [1] [1] Receive data being received becomes invalid. Yes [2] Includes module stop mode. Read receive data in RDR RE = 0 Transition to software standby mode, etc. [2] Exit from software standby mode, etc. Change operating mode? No Yes Initialization RE = 1 Figure 13.43 Sample Flowchart for Mode Transition during Reception Page 468 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 13 Serial Communication Interface 13.10.6 Switching from SCK Pin Function to Port Pin Function When switching the SCK pin function to the output port function (high-level output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. End of serial data transmission 2. TE bit = 0 3. C/A bit = 0 ... switchover to port output 4. Occurrence of low-level output (see figure 13.
H8S/2215 Group Section 13 Serial Communication Interface Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown. 1. End of serial data transmission 2. TE bit = 0 3. CKE1 bit = 1 4. C/A bit = 0 ... switchover to port output 5.
H8S/2215 Group Section 14 Boundary Scan Function Section 14 Boundary Scan Function This LSI incorporates a boundary scan function, which is a serial I/O interface based on the JTAG (Joint Test Action Group, IEEEStd.1149.1 and IEEE Standard Test Access Port and Boundary Scan Architecture). Figure 14.1 shows the block diagram of the boundary scan function. 14.
H8S/2215 Group Section 14 Boundary Scan Function BSCANR (Boundary scan cell chain) IDCODE MUX TDO MUX BYPASS TDI INSTR TCK TMS TAP controller TRST Legend: BSCANR: IDCODE: BYPASS: INSTR: TAP: Boundary scan register IDCODE register BYPASS register Instruction register Test access port Figure 14.1 Block Diagram of Boundary Scan Function Page 472 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group 14.2 Section 14 Boundary Scan Function Pin Configuration Table 14.1 shows the I/O pins used in the boundary scan function. Table 14.1 Pin Configuration Pin Name I/O TMS Input Function Test Mode Select Controls the TAP controller which is a 16-state Finite State Machine. The TMS input value at the rising edge of TCK determines the status transition direction on the TAP controller. The TMS is fixed high when the boundary scan function is not used.
H8S/2215 Group Section 14 Boundary Scan Function 14.3 Register Descriptions The boundary scan function has the following registers. These registers cannot be accessed by the CPU. • Instruction register (INSTR) • IDCODE register (IDCODE) • BYPASS register (BYPASS) • Boundary scan register (BSCANR) 14.3.1 Instruction Register (INSTR) INSTR is a 3-bit register. At initialization, this register is specified to IDCODE mode.
H8S/2215 Group Section 14 Boundary Scan Function EXTEST: The EXTEST instruction is used to test external circuits when this LSI is installed on the print circuit board. If this instruction is executed, output pins are used to output test data (specified by the SAMPLE/PRELOAD instruction) from the boundary scan register to the print circuit board, and input pins are used to input test results.
H8S/2215 Group Section 14 Boundary Scan Function 14.3.2 IDCODE Register (IDCODE) IDCODE is a 32-bit register. If INSTR is set to IDCODE mode, IDCODE is connected between TDI and TDO. The HD64F2215 and H8S/2215U output fixed code H'0002200F, HD6432215B output fixed code H'001B200F, HD6432215C output fixed code H'001C200F, HD64F2215R, HD64F2215RU and HD64F2215CU output fixed code H'08030447, and HD64F2215T and HD64F2215TU output fixed code H'08031447, respectively, from the TDO.
H8S/2215 Group 14.3.4 Section 14 Boundary Scan Function Boundary Scan Register (BSCANR) BSCAN is a 217-bit shift register assigned on the pins to control input/output pins. The I/O pins consists of three bits (IN, Control, OUT), input pins 1 bit (IN), and output pins 1 bit (OUT) of shift registers. The boundary scan test based on the JTAG standard can be performed by using instructions listed in table 14.2. Table 14.4 shows the correspondence between the LSI pins and boundary scan registers.
H8S/2215 Group Section 14 Boundary Scan Function Table 14.4 Correspondence between LSI Pins and Boundary Scan Register TFP-120, TFP-120V Pin No. BP-112, BP-112V Pin No.
H8S/2215 Group Section 14 Boundary Scan Function TFP-120, TFP-120V Pin No. BP-112, BP-112V Pin No. Pin Name I/O Bit Name 4 D4 PD2/D10 IN 186 Control 185 5 6 7 8 9 11 13 14 15 16 C2 C1 D3 D2 D1 E3 E2 F3 F1 F2 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 14 Boundary Scan Function TFP-120, TFP-120V Pin No. BP-112, BP-112V Pin No.
H8S/2215 Group Section 14 Boundary Scan Function TFP-120, TFP-120V Pin No. BP-112, BP-112V Pin No. Pin Name I/O Bit Name 30 J3 PA0/A16 IN 120 Control 119 31 32 33 35 36 37 38 39 40 41 K2 L2 H4 K3 L3 J4 K4 L4 H5 J5 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 14 Boundary Scan Function TFP-120, TFP-120V Pin No. BP-112, BP-112V Pin No.
H8S/2215 Group Section 14 Boundary Scan Function TFP-120, TFP-120V Pin No. BP-112, BP-112V Pin No. Pin Name I/O Bit Name 86 C11 PF1/BACK IN 56 Control 55 87 88 89 90 91 92 93 94 96 97 D9 C10 B11 C9 B10 A10 D8 B9 A9 C8 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 14 Boundary Scan Function TFP-120, TFP-120V Pin No. BP-112, BP-112V Pin No.
H8S/2215 Group Section 14 Boundary Scan Function 14.4 Boundary Scan Function Operation 14.4.1 TAP Controller Figure 14.3 shows the TAP controller status transition diagram, based on the JTAG standard. Test-Logic-Reset 0 1 Run-Test/Idle 1 Select-DR 0 1 0 0 1 Select-IR 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 1 Update-DR 0 1 Capture-IR 0 1 Shift-IR 1 0 Exit1-IR 1 Pause-DR 0 1 0 1 Exit2-DR 0 1 Update-IR 0 Pause-IR 0 1 1 0 Exit2-IR 0 Figure 14.
H8S/2215 Group Section 14 Boundary Scan Function 14.5 Usage Notes 1. When using the boundary scan function, clear TRST to 0 at power-on and after the tRESW time has elapsed set TRST to 1 and set TCK, TMS, and TDI appropriately. During normal operation when the boundary scan function is not used, set TCK, TMS, and TDI to Hi-Z, clear TRST to 0 at power-on, and after the tRESW time has elapsed set TRST to 1 or to Hi-Z.
H8S/2215 Group Section 14 Boundary Scan Function 5. If a pin with pull-up function is SAMPLEed with pull-up function enabled, the corresponding IN register is set to 1. In this case, the corresponding Control register must be cleared to 0. 6. If a pin with open-drain function is SAMPLEed while its open-drain function is enabled and while the corresponding OUT register is set to 1, the corresponding Control register is cleared to 0 (the pin status is Hi-Z).
Section 14 Boundary Scan Function Page 488 of 846 H8S/2215 Group REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Section 15 Universal Serial Bus Interface (USB) This LSI incorporates a USB function module complying with USB standard version 1.1. Figure 15.1 shows the block diagram of the USB. 15.1 Features • USB standard version 2.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) • Maximum Configuration, InterfaceNumber, and AlternateSetting configuration specifications of this LSI H8S/2215: EP0 Configuration 1 ----- InterfaceNumber 0 to 2 ----- AlternateSetting 0 to 7 ----- EP1 to EP8 H8S/2215R, H8S/2215T and H8S/2215C: EP0 Configuration 1 ----- InterfaceNumber 0 to 3 ----- AlternateSetting 0 to 7 ----- EP1 to EP8 • Start of frame (SOF) marker function ⎯ SOF interrupt occurs every 1 ms even though broken SOF received
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) USB [Power mode selection] 1288-byte FIFO EP0s EP2i EP4i EP0i EP2o EP4o EP0o EP3i EP5i EP1i EP3o UBPM [Connection/disconnection] VBUS [Suspend] USPND [Interrupt request signal] [Power supply] IRQ6 DrVcc EXIRQ0, EXIRQ1 [DMA internal request signal] DREQ0, DREQ1 DrVss Registers [Internal bus] Peripheral data bus Peripheral address bus Internal transceiver Interface [Data] USD+ USD- Rs Rs D+ D- Peripheral bus control signal
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.2 Input/Output Pins Table 15.1 shows the USB pin configuration. Table 15.
H8S/2215 Group 15.3 Section 15 Universal Serial Bus Interface (USB) Register Descriptions The USB has the following registers for each channel.
Section 15 Universal Serial Bus Interface (USB) H8S/2215 Group • USB interrupt enable register 3 (UIER3) • USB interrupt selection register 0 (UISR0)* • USB interrupt selection register 1 (UISR1)* • USB interrupt selection register 2 (UISR2)* • USB interrupt selection register 3 (UISR3) • USB data status register (UDSR)* • USB configuration value register (UCVR) • USB time stamp register H, L (UTSRH, L) • USB test register 0 (UTSTR0) • USB test register 1 (UTSTR1) • USB test register 2 (UTSTR2) • USB test
H8S/2215 Group 15.3.1 Section 15 Universal Serial Bus Interface (USB) USB Endpoint Information Registers 00_0 to 22_4 (UEPIR00_0 to UEPIR22_4) UEPIR is used to set 23 kinds of endpoint (EPINFO data). EPINFO data for each endpoint consists of 40 bits (five bytes). 115 bytes of endpoint data for all UEPIR00_0 to UEPIR22_4 registers must be written after the UDC interface software reset has been cancelled (the UIFST bit of the UCTLR register is cleared to 0).
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) • UEPIRnn_0 Bit Bit Name Initial Value R/W Description 7 to 4 D39 to D36 — R/W Endpoint number (4-bit configuration, settable values: 0 to 8) 0000: Control transfer (EP0) 0001 to 1000: Other than Control transfer (EP1 to EP8) There are restrictions on settable endpoint numbers according to the Interface number and Alternate number to which the endpoint belongs. Restriction 1: Set different endpoint numbers under one Alternate.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) • UEPIRnn_1 Bit Bit Name Initial Value R/W Description 7 to 5 D31 to D29 — R/W Alternate number to which endpoint belongs (3-bit configuration, settable values: 0 to 7) 000: Control transfer 000 to 111: Other than Control transfer 4 D28 — R/W Endpoint transfer type (2-bit configuration) 3 D27 — R/W 00: Control (UEPIR00) 01: Isochronous (UEPIR04 to UEPIR19) 10: Bulk (UEPIR02, UEPIR03, UEPIR20, UEPIR21) 11: Interrupt (UEPIR01,
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) • UEPIRnn_3 Bit Bit Name Initial Value R/W Description 7 to 0 D15 to D8 — R/W Endpoint internal address (D15 to D0 16-bit configuration) Set UEPIR00_3, UEPIR00_4 = H'0000 Set UEPIR01_3, UEPIR01_4 = H'0001 : Set UEPIR21_3, UEPIR21_4 = H'0015 Set UEPIR22_3, UEPIR22_4 = H'0016 • UEPIRnn_4 Bit Bit Name Initial Value R/W Description 7 to 0 D7 to D0 — R/W Endpoint internal address (D15 to D0 16-bit configuration) Set UEPIR00_3,
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Note that endpoint data information must match the corresponding descriptor information to be returned to the host . Otherwise, the USB cannot operate correctly. For example, if the descriptor information is returned as 16 bytes while the maximum packet size of the EPINFO data is eight bytes, the host attempts to access the EPINFO data in 16 byte units and cannot operate correctly.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Table 15.2 EPINFO Data Settings EPINFO Data Settings Based on Bluetooth Standard Register No.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) EPINFO Data Settings Based on Bluetooth Standard Register No.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.2 USB Control Register (UCTLR) UCTLR is used to select USB data input/output pin and USB operating clock, specify SOF marker function, and controls the USB module reset. UCTLR can be read from or written to even in USB module stop mode. For details on UCTLR setting procedure, refer to section 15.5, Communication Operation.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Bit Bit Name Initial Value R/W Description 5 UCKS3 0 R/W USB Operating Clock Selection 3 to 0 4 UCKS2 0 R/W 3 UCKS1 0 R/W 2 UCKS0 0 R/W Select the USB operating clock (48 MHz). When UCKS0 to UCKS3 are 0000, both the 48-MHz oscillator and internal PLL circuit stop and USB operating clock must be selected according to the clock source.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Bit Bit Name Initial Value R/W Description 5 UCKS3 0 R/W 4 UCKS2 0 R/W 3 UCKS1 0 R/W 1000: Uses a clock supplied by the 48-MHz external clock (EXTAL48 pin input) directly. The PLL stops. The USB operating clock stabilization time is 246 to 200 μs. 2 UCKS0 0 R/W 1001 (H8S/2215): Reserved 1001 (H8S/2215R, H8S/2215T and H8S/2215C): Uses the clock supplied by the 48-MHz external clock (EXTAL48 pin input) directly.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Bit Bit Name Initial Value R/W Description 1 UIFRST 1 USB Interface Software Reset R/W Controls USB module internal reset. When the UIFRST bit is set to 1, the USB internal modules other than UCTLR, UIER3, and the CK48 READY bit of UIFR3 are all reset. At initialization, the UIFRST bit must be cleared to 0 after the USB operating clock stabilization time has passed following USB module stop mode cancellation.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.3 USB DMAC Transfer Request Register (UDMAR) UDMAR is set when data transfer by means of a USB request of the on-chip DMAC is performed for data registers UEDR2i, UEDR2o, UEDR4i, and UEDR4o corresponding to EP2i, EP2o, EP4i, and EP4o used for Bulk transfer, respectively. DMAC transfer request sources specified in UDMAR must be two or less.
H8S/2215 Group 15.3.4 Section 15 Universal Serial Bus Interface (USB) USB Device Resume Register (UDRR) UDRR indicates remote wakeup according to the host enable/disable state and enables or disables remote wakeup of the USB modules in the suspend state. Bit Bit Name 7 to 2 — Initial Value R/W All 0 R Description Reserved These bits are always read as 0 and cannot be modified. 1 RWUPs 0 R Remote Wakeup Status Indicates the enabled or disabled state of remote wakeup by the host.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.5 USB Trigger Register 0 (UTRG0) UTRG0 generates one-shot triggers to the FIFO for each endpoint EP0 to EP2. For information on accessing this register, see 2.9.4, Accessing Registers Containing Write-Only Bits. Bit Bit Name Initial Value R/W 7, 6 — All 0 R Description Reserved These bits are always read as 0 and cannot be modified.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Bit Bit Name Initial Value R/W 0 EP0sRDFN 0 W Description EP0s Read Completion 0: Performs no operation. A NAK handshake is returned in response to transmit/receive requests from the host in the data stage until 1 is written to this bit. 1: Writes 1 to this bit after reading data for EP0s OUT FIFO. After receiving the setup command, this trigger enables the next packet to be received by the EP0i and EP0o in the data stage.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.7 USBFIFO Clear Register 0 (UFCLR0) UFCLR0 is a one-shot register used to clear the FIFO for each end point from EP0 to EP3. Writing 1 to a bit clears the data in the corresponding FIFO. For IN FIFO, writing 1 to a bit in UFCLR0 clears the data for which the corresponding PKTE bit in UTRG0 is cleared to 0 after data write, or data that is validated by setting the corresponding PKTE bit in UTRG0.
H8S/2215 Group Note: When DMA transfers are enabled (EP2oT1 bit set to 1 and EP2oT0 bit set to 0 or 1 in the UDMAR register), the data in the FIFO is cannot be cleared by writing 1 to EP2oCLR. To clear the data in the FIFO, first disable DMA transfers (clear the EP2oT1 and EP2oT0 bits in the UDMAR register to 0) and then write 1 to EP2oCLR. * 15.3.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.9 USB Endpoint Stall Register 0 (UESTL0) UESTL0 is used to forcibly stall the endpoints for EP0 to EP3. While the bit is set to 1, the corresponding endpoint returns a stall handshake to the host. However, note that EP3 (Isochronous transfer) does not return a stall handshake. The stall bit for endpoint 0 (EP0STL) is cleared automatically on reception of 8-bit command data for which decoding is performed by the function.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.10 USB Endpoint Stall Register 1 (UESTL1) UESTL1 is used to forcibly stall the endpoints for EP4 and EP5. In addition, UESTL1 can cancel all endpoint stall states. While the bit is set to 1, the corresponding endpoint returns a stall handshake to the host. For details, refer to section 15.5.11, Stall Operations. Bit Bit Name Initial Value R/W Description 7 SCME 0 Reserved R/W The write value should always be 0.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.12 USB Endpoint Data Register 0i (UEDR0i) UEDR0i is a data register for endpoint 0i (for Control_in transfer). UEDR0i stores data to be sent to the host. The number of data items to be written continuously must be the maximum packet size or less. UEDR0i is a byte register to which 4-byte address area is assigned. Accordingly, UEDR0i allows the user to write 2-byte or 4-byte data by word transfer or longword transfer.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.15 USB Endpoint Data Register 2i (UEDR2i) UEDR2i is a data register for endpoint 2i (for Bulk_in transfer). UEDR2i stores data to be sent to the host. The number of data items to be written continuously must be the maximum packet size or less. UEDR2i is a byte register to which 4-byte address area is assigned. Accordingly, UEDR2i allows the user to write 2-byte or 4-byte data by word transfer or longword transfer.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.18 USB Endpoint Data Register 3o (UEDR3o) UEDR3o is a data register for endpoint 3o (for Isochronous_out transfer). UEDR3o stores data received from the host. The number of data items to be read must be specified by UESZ3o. When 1 byte is read from UEDR3o, UESZ3o is decremented by 1. All data items must be read before the next SOF packet is received. UEDR3o is a byte register to which 4-byte address area is assigned.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.21 USB Endpoint Data Register 5i (UEDR5i) UEDR5i is a data register for endpoint 5i (for Interrupt_in transfer). UEDR5i stores data to be sent to the host. The number of data items to be written continuously must be the maximum packet size or less. UEDR5i is a byte register to which 4-byte address area is assigned. Accordingly, UEDR5i allows the user to write 2-byte or 4-byte data by word transfer or longword transfer.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.24 USB Endpoint Receive Data Size Register 3o (UESZ3o) UESZ3o is the receive data size register for endpoint 3o (for Isochronous_out transfer). UESZ3o indicates the number of bytes of data to be received from the host. Note that UESZ3o is decremented by 1 every time when 1 byte is read from UEDR3o. The FIFO for endpoint 3o (for Isochronous_out transfer) has a dual-FIFO configuration.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Bit Bit Name Initial Value R/W 7 BRST 0 Description R/(W)* Bus Reset Set to 1 when the bus reset signal is detected on the USB bus. The corresponding interrupt output is EXIRQ0 or EXIRQ1. Note that BRST is also set to 1if D+ is not pulled-up during USB cable connection. 6 5 — EP1iTR 0 R Reserved 0 This bit is always read as 0 and cannot be modified.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.27 USB Interrupt Flag Register 1 (UIFR1) (Only in H8S/2215) UIFR1 is an interrupt flag register indicating the EP2i, EP2o, EP3i, and EP3o. If the corresponding bit is set to 1, the corresponding EXIRQ0 or EXIRQ1 interrupt is requested from the CPU. EP2iTR and EP3iTR flags can cleared by writing 0 to them. Writing 1 to them is invalid and causes no operation.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Bit Bit Name Initial Value R/W Description 3 — 0 Reserved R This bit is always read as 0 and cannot be modified. 2 EP2oREADY 0 R EP2o Data Ready EP2o FIFO has a dual-FIFO configuration. This flag is set if there is a valid data in at least one EP2o FIFO. This flag is cleared to 0 if there is no valid data in EP2o FIFO. This flag is a status flag and cannot be cleared. The corresponding interrupt output is EXIRQ0 or EXIRQ1.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.28 USB Interrupt Flag Register 1 (UIFR1) (Only in H8S/2215R, H8S/2215T and H8S/2215C) UIFR1 is an interrupt flag register indicating the EP2i, EP2o, EP3i, and EP3o. If the corresponding bit is set to 1, the corresponding EXIRQ0 or EXIRQ1 interrupt is requested from the CPU. EP2iTR and EP3iTR flags can cleared by writing 0 to them. Writing 1 to them is invalid and causes no operation.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Bit Bit Name Initial Value R/W Description 3 EP2iALL 1 EP2i FIFO All Empty Status R EMPTYS 2 EP2i FIFO has a dual FIFO configuration. This flag is set to 1 if both FIFOs are empty. (Corresponds to a UDSR/EP2iDE negative-polarity signal.) EP2oREADY 0 R EP2o Data Ready EP2o FIFO has a dual-FIFO configuration. This flag is set if there is a valid data in at least one EP2o FIFO.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.29 USB Interrupt Flag Register 2 (UIFR2) (Only in H8S/2215) UIFR2 is an interrupt flag register indicating the state of EP4i, EP4o, and EP5i. If the corresponding bit is set to 1, the corresponding EXIRQ0 or EXIRQ1 interrupt is requested to the CPU. EP4iTR EP5iTS and EP4iTR flags can cleared by writing 0 to them. Writing 1 to them is invalid and causes no operation.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.30 USB Interrupt Flag Register 2 (UIFR2) (Only in H8S/2215R, H8S/2215T and H8S/2215C) UIFR2 is an interrupt flag register indicating the state of EP4i, EP4o, and EP5i. If the corresponding bit is set to 1, the corresponding EXIRQ0 or EXIRQ1 interrupt is requested to the CPU. EP4iTR EP5iTS and EP4iTR flags can cleared by writing 0 to them. Writing 1 to them is invalid and causes no operation.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Bit Bit Name Initial Value R/W 1 EP4iTR 0 Description R/(W)* EP4i Transfer Request Set to 1 if the EP4i FIFO is empty when an IN token is sent form the host to EPi4. The corresponding interrupt output is EXIRQ0 or EXIRQ1. 0 EP4iEMPTY 1 R EP4i FIFO Empty EP4i FIFO has a dual-FIFO configuration. This flag is set if at least one EP4i FIFO is empty. This flag is cleared to 0 if EP4i FIFO is full.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.31 USB Interrupt Flag Register 3 (UIFR3) UIFR3 is an interrupt flag register indicating the USB status. If the corresponding bit is set to 1, the corresponding EXIRQ0, EXIRQ1, or IRQ6 interrupt is requested from the CPU. VBUSi, SPRSi, SETI, SETC, SOF, and CK48READY flags can be cleared by writing 0. Writing 1 to them is invalid and causes no operation.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Bit Bit Name Initial Value R/W Description 3 SPRSs 0 Suspend/Resume Status R Indicates the suspend/resume status and cannot request an interrupt. 0: Indicates that the bus is in the normal state. 1: Indicates that the bus is in the suspend state. 2 SPRSi 0 R/(W)* Suspend/Resume Interrupt Set to 1 if a transition from normal state to suspend state or suspend state to normal state has occurred.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.32 USB Interrupt Enable Register 0 (UIER0) UIER0 enables the interrupt request indicated in the interrupt flag register 0 (UIFR0). When an interrupt flag is set while the corresponding bit in UIER0 is set to 1, an interrupt is requested by asserting the corresponding EXIRQ0 or EXIRQ1 pin. Either EXIRQ0 or EXIRQ1 must be selected by the interrupt select register 0 (UISR0).
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.34 USB Interrupt Enable Register 1 (UIER1) (Only in H8S/2215R, H8S/2215T and H8S/2215C) UIER1 enables the interrupt request indicated in the interrupt flag register 1 (UIFR1). When an interrupt flag is set while the corresponding bit in UIER1 is set to 1, an interrupt is requested by asserting the corresponding EXIRQ0 or EXIRQ1 pin. Either EXIRQ0 or EXIRQ1 must be selected by the interrupt select register 1 (UISR1).
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.36 USB Interrupt Enable Register 2 (UIER2) (Only in H8S/2215R, H8S/2215T and H8S/2215C) UIER2 enables the interrupt request indicated in the interrupt flag register 2 (UIFR2). When an interrupt flag is set while the corresponding bit in UIER2 is set to 1, an interrupt is requested by asserting the corresponding EXIRQ0 or EXIRQ1 pin. Either EXIRQ0 or EXIRQ1 must be selected by the interrupt select register 2 (UISR2).
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Bit Bit Name 7 Initial Value R/W Description CK48READYE 1 R/W Enables the CK48READY interrupt 6 SOFE 0 R/W Enables the SOF interrupt 5 SETCE 0 R/W Enables the SETC interrupt 4 SETIE 0 R/W Enables the SETI interrupt 3 — 0 R Reserved This bit is always read as 0. 2 SPRSiE 0 R/W Enables the SPRSi interrupt (only for IRQ6) 1 — 0 R Reserved 0 VBUSiE 0 R/W This bit is always read as 0.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.39 USB Interrupt Select Register 1 (UISR1) (Only in H8S/2215) UISR1 selects the EXIRQ pin to output interrupt request indicated in the interrupt flag register 1 (UIFR1). When a bit in UIER1 corresponding to the UISR1 bit is cleared to 0, an interrupt request is output to EXIRQ0. When a bit in UIER1 corresponding to the UISR1 bit is set to 1, an interrupt request is output to EXIRQ1.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.41 USB Interrupt Select Register 2 (UISR2) (Only in H8S/2215) UISR2 selects the EXIRQ pin to output interrupt request indicated in the interrupt flag register 2 (UIFR2). When a bit in UIER2 corresponding to the UISR2 bit is cleared to 0, an interrupt request is output to EXIRQ0. When a bit in UIER2 corresponding to the UISR2 bit is set to 1, an interrupt request is output to EXIRQ1.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.43 USB Interrupt Select Register 3 (UISR3) UISR3 selects the EXIRQ pin to output interrupt request indicated in the interrupt flag register 3 (UIFR3). When a bit in UIER3 corresponding to the UISR3 bit is cleared to 0, an interrupt request is output to EXIRQ0. When a bit in UIER3 corresponding to the UISR3 bit is set to 1, an interrupt request is output to EXIRQ1.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.44 USB Data Status Register (UDSR) UDSR indicates whether the IN FIFO data registers (EP0i, EP1i, EP2i, EP4i, and EP5i) contain valid data or not. A bit in USDR is set when data written to the corresponding IN FIFO becomes valid after the corresponding PKTE bit in UTRG is set to 1. A bit in USDR is cleared when all valid data is sent to the host.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.45 USB Configuration Value Register (UCVR) UCVR stores the Configuration value, Interface Number value and Alternate Setting value when the Set_Configuration and Set_Interface commands are received from the host. Bit Bit Name Initial Value R/W 7, 6 — All 0 R Description Reserved These bits are always read as 0 and cannot be modified.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.46 USB Time Stamp Registers H, L (UTSRH, UTSRL) UTSRH and UTSRL store the current time stamp values. The time stamp values in UTSRH and UTSRL are modified when the SOF flag in UIFR3 is set to 1. UTSRH combined with UTSRL can also be handled as a 16-bit register. The USB module has an 8-bit bus. The upper byte of UTSRH can be read directly, while the lower byte of UTSRL is read through an 8-bit temporary register.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.47 USB Test Register 0 (UTSTR0) UTSTR0 controls internal or external transceiver output signals. After clearing UCTLR/UIFRST and UDCRST to 0, setting the PTSTE bit to 1 enable user setting of transceiver output. Table 15.3 shows the relationship between UTSTR0 settings and pin outputs.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Table 15.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.48 USB Test Register 1 (UTSTR1) UTSTR1 allows internal or external transceiver input signals to be monitored. When the FADSEL bit of UCTLR is set to 0, internal transceiver input signals can be monitored. When the FADSEL bit is FADSEL = 1, external transceiver input signals can be monitored. Table 15.4 shows the relationship between UTSTR1 settings and pin inputs.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Table 15.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.3.49 USB Test Registers 2 and A to F (UTSTR2, UTSRA to UTSRF) UTSTR2 and UTSRTA to UTSRTF are test registers and cannot be written to. 15.3.50 Module Stop Control Register B (MSTPCRB) Bit Bit Name Initial Value R/W Description 7 MSTPB7 1 R/W Module Stop Bits 6 MSTPB6 1 R/W 5 MSTPB5 1 R/W For details, refer to section 22.1.2, Module Stop Control Registers A to C (MSTPCRA to MSTPCRC).
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Table 15.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Register Bit Interrupt Request Signal DMAC Activation by USB Request*9 UIFR2 0 Transfer Mode Bulk_in transfer (EP4i) 1 EP4i FIFO empty EXIRQ0 or EXIRQ1 DREQ0 or DREQ1*4 EP4iTR EP4i transfer request EXIRQ0 or EXIRQ1 × EP4o data ready EXIRQ0 or EXIRQ1 DREQ0 or DREQ1*5 Bulk_out transfer EP4oREADY (EP4o) 3 Bulk_in transfer*7 EP4iALLEMPTYS*8 EP4i all empty states*7 (EP4i) EXIRQ0 or EXIRQ1*7 ×* 7 4 Interrupt_in transfer (EP5i)
Section 15 Universal Serial Bus Interface (USB) H8S/2215 Group • EXIRQ0 signal The EXIRQ0 signal requests interrupt sources for which the corresponding bits in interrupt select registers 0 to 3 (UISR0 to UISR3) are cleared to 0. The EXIRQ0 is driven low if a corresponding bit in the interrupt flag register is set to 1. • EXIRQ1 signal The EXIRQ1 signal requests interrupt sources for which the corresponding bits in interrupt select registers 0 to 3 (UISR0 to UISR3) are cleared to 0.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.5 Communication Operation 15.5.1 Initialization The USB must be initialized as described in the flowchart in figure 15.3.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.5.2 USB Cable Connection/Disconnection (1) USB Cable Connection (When USB Module Stop or Software Standby Is Not Used) If the USB cable enters the connection state from the disconnection state in an application (self powered) where USB module stop or software standby mode is not used, perform the operation shown in figure 15.4. In bus-powered mode, perform the operation described in note 2.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) (2) USB Cable Connection (When USB Module Stop or Software Standby Is Used) If the USB cable enters the connection state from disconnection state an application (self powered) where USB module stop or software standby mode is used, perform the operation as shown in figure 15.5.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) (3) USB Cable Disconnection (When USB Module Stop or Software Standby Is Not Used) If the USB cable enters the disconnection state from the connection state in an application (self powered) where USB module stop or software standby mode is not used, perform the operation shown in figure 15.6. In bus-powered mode, the power is automatically turned off when the USB cable is disconnected and the following processing is not required.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) (4) USB Cable Disconnection (When USB Module Stop or Software Standby Is Used) If the USB cable enters the disconnection state from the connection state in an application (self powered) where USB module stop or software standby mode is used, perform the operation shown in figure 15.7.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.5.3 Suspend and Resume Operations (1) Suspend and Resume Operations Figures 15.8 and 15.9 are flowcharts of the suspend and resume operations. If the USB bus enters the suspend state from a non-suspend state, or if it enters a non-suspend state from the suspend state due to a resume signal from up-stream, perform the operations shown below.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) (2) Suspend and Resume Interrupt Processing Figure 15.9 is a flowchart of suspend and resume interrupt processing.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) (3) Suspend and Remote-Wakeup Operations Figures 15.10 and 15.11 are flowcharts of the suspend and remote-wakeup operations. If the USB bus enters a non-suspend state from the suspend state due to a remote-wakeup signal from this function, perform the operations shown below.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) (4) Remote-Wakeup Interrupt Processing Figure 15.11 is a flowchart of remote-wakeup interrupt processing.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.5.4 Control Transfer The control transfer consists of three stages; setup, data (sometimes omitted), and status, as shown in figure 15.12. The data stage consists of multiple bus transactions. Figures 15.13 to 15.17 show operation flows in each stage. Setup stage Control-in Control-out No data Data stage SETUP (0) IN (1) IN (0) DATA0 DATA1 DATA0 SETUP (0) OUT (1) OUT (0) DATA0 DATA1 DATA0 Status stage ... ...
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) (1) Setup Stage USB function Firmware Receive SETUP token Receive 8-byte command data in UEDR0s Command to be processed by firmware? No Automatic processing by this module Yes Set setup command receive complete flag (SetupTS in UIFR0 = 1) To data stage EXIRQx Clear SetupTS flag (SetupTS in UIFR0 = 0) Clear EP0iFIFO (EP0iCLR in UFCLR0 = 1) Clear EP0oFIFO (EP0oCLR in UFCLR0 = 1) Read 8-byte data from UEDR0s Decode command data Determ
Section 15 Universal Serial Bus Interface (USB) H8S/2215 Group (2) Data Stage (Control-In) The firmware first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is intransfer, one packet of data to be sent to the host is written to the FIFO.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) USB function Firmware Receive IN token From setup stage 1 written to EP0sRDFN in UTRG0? Write data to USB endpoint data register 0i (UEDR0i) No NAK Yes Valid data in EP0iFIFO? Write 1 to EP0i packet enable bit (EP0iPKTE in UTRG0 = 1) No NAK Yes Transmit data to host ACK Set EP0i transmit complete flag (EP0iTS in UIFR0 = 1) EXIRQx Clear EP0i transmit complete flag (EP0iTS in UIFR0 = 0) Write data to USB endpoint data register 0i
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) (3) Data Stage (Control-Out) The firmware first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is outtransfer, the application waits for data from the host, and after data is received (EP0oTS of UIFR0 is set to 1), reads data from the FIFO.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) (4) Status Stage (Control-In) The control-in status stage starts with an OUT token from the host. The firmware receives 0-byte data from the host, and ends control transfer.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) (5) Status Stage (Control-Out) The control-out status stage starts with an IN token from the host. When an IN-token is received at the start of the status stage, there is not yet any data in the EP0iFIFO, and so an EP0i transfer request interrupt is generated. The application recognizes from this interrupt that the status stage has started.
H8S/2215 Group 15.5.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.5.6 Bulk-In Transfer (Dual FIFOs) (EP2i Is specified as Endpoint) EP2i has two 64-byte FIFOs, but the user can perform data transmission and transmit data writes without being aware of this dual-FIFO configuration. However, one data write is performed for one FIFO. For example, even if both FIFOs are empty, it is not possible to perform EP2iPKTE at one time after consecutively writing 128 bytes of data.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) USB function Firmware Receive IN token No Valid data in EP2iFIFO? Is there data to be transmitted to the host? NAK Yes No Yes Write 1 to EP2iFIFO empty enable (EP2iEMPTYE in UIER1 = 1) Transmit data to host ACK Yes Space in EP2iFIFO? Set EP2iFIFO empty status (EP2iEMPTY in UIFR1 = 1) EXIRQx EP2iEMPTY in UIFR1 interrupt No Clear EP2iFIFO empty status (EP2iEMPTY in UIFR1 = 0) Write one packet of data to USB endpoint data regist
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.5.7 Bulk-Out Transfer (Dual FIFOs) (EP2o Is specified as Endpoint) EP2o has two 64-byte FIFOs, but the user can perform data reception and receive data reads without being aware of this dual-FIFO configuration. When one FIFO is full after reception is completed, the UIFR1/EP2oREADY bit is set.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) USB function Firmware Receive OUT token Space in EP2oFIFO? No NAK Yes Transmit data from host ACK EXIRQx Set EP2o data ready status (EP2oREADY in UIFR1 = 1) Read USB endpoint receive data size register 2o (UESZ2o) Read data from USB endpoint data register 2o (UEDR2o) Write 1 to EP2o read complete bit (EP2oRDFN in UTRG0 = 1) Both EP2oFIFOs empty? No EXIRQx Yes Clear EP2o data ready status (EP2oREADY in UIFR1 = 0) Figure 15.
Section 15 Universal Serial Bus Interface (USB) 15.5.8 H8S/2215 Group Isochronous–In Transfer (Dual-FIFO) (When EP3i Is Specified as Endpoint) EP3i has two 128-byte (maximum) FIFOs, however the user can perform data transmission and transmit data writes without being aware of this dual-FIFO configuration. In isochronous transfer, as a transmission is performed once a frame (1 ms), the hardware automatically switches FIFOs when the hardware receives the SOF.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) USB function Firmware EXIRQx Receive SOF Valid data in FIFO B has been transferred? No EP3i IN token not received (Set EP3iTF in UIFR1 to 1) Yes Clear the SOF packet detection flag (Clear SOF in UIFR3 to 0) Read USB time stamp registers H and L (UTSRH and UTSRL) Switch to FIFO A FIFO A FIFO B Receive IN token Valid data in FIFO A has been transferred? No Set EP3i transfer request flag (Set EP3iTR in UIFR1 to 1) Write 1-packet d
Section 15 Universal Serial Bus Interface (USB) 15.5.9 H8S/2215 Group Isochronous–Out Transfer (Dual-FIFO) (When EP3o Is Specified as Endpoint) EP3o has two 128-byte (maximum) FIFOs, however the user can perform data transmission and transmit data writes without being aware of this dual-FIFO configuration. In isochronous transfer, as a transmission is performed once a frame (1 ms), the hardware automatically switches FIFOs when the hardware receives the SOF.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) USB function Firmware EXIRQx Receive SOF Switch to FIFO B-side UIFR1/EP3oTS, EP3oTF update Start of Frame Clear the SOF packet detection flag (Clear SOF in UIFR3 to 0) Read USB time stamp registers H and L (UTSRH and UTSRL) FIFO B FIFO A Receive OUT token Read EP3o statis (Read EP3oTS and EP3oTF in UIFR1) Receive data from the host Receive data error? Read USB endpoint receive data size register 3o (UESZ3o) No Read data from the US
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.5.10 Processing of USB Standard Commands and Class/Vendor Commands (1) Processing of Commands Transmitted by Control Transfer A command transmitted from the host by control transfer may require decoding and execution of command processing by the firmware. Whether or not command decoding is required by the firmware is indicated in table 15.6 below. Table 15.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.5.11 Stall Operations (1) Overview This section describes stall operations in the USB function module. There are two cases in which the USB function module stall function is used: 1. When the firmware forcibly stalls an endpoint for some reason 2.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) (1) Transition from normal operation to stall USB function module (1-1) USB EPnSTL 0→1 Internal status bit 0 1. Set EPnSTL to 1 by firmware (1-2) Reference Transaction request EPnSTL 1 Internal status bit 0 1. Receive IN/OUT token from the host 2. Refer to EPnSTL To (1-3) (1-3) Stall STALL handshake EPnSTL 1 (SCME = 0) Internal status bit 0→1 To (2-1) or (3-1) 1. SCME is set to 1 2. EPnSTL is set to 1 3.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) (3) Automatic Stall by USB Function Module When a stall setting is made with the Set Feature command, when the information of this module differs from that returned to the host by the Get Descriptor, or in the event of a USB specification violation, the USB function module automatically sets the internal status bit for the relevant endpoint without regard to EPnSTL, and returns a stall handshake (1-1 in figure 15.24).
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) (1) Transition from normal operation to stall USB function module (1-1) STALL handshake Internal status bit 0→1 EPnSTL 0 To (2-1) or (3-1) 1. In case of USB specification violation, USB function module stalls endpoint automatically. (2) When transaction is performed when internal status bit is set (2-1) Transaction request Internal status bit 1 EPnSTL 0 Internal status bit 1 EPnSTL 0 1. Receive IN/OUT token from the host 2.
H8S/2215 Group 15.6 Section 15 Universal Serial Bus Interface (USB) DMA Transfer Specifications Two methods of USB request and auto request are available for the DMA transfer of USB data. 15.6.1 DMA Transfer by USB Request (1) Overview Only normal mode in full address mode (cycle steal mode) supports the transfer by a USB request of the on-chip DMAC. Endpoints that can be transferred by the on-chip DMAC are EP2 and EP4 in Bulk transfer (corresponding registers are UEDR2i, UEDR2o, UEDR4i, and UEDR4o).
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) This kind of internal processing is performed when the currently selected data FIFO becomes full. Accordingly, this processing is automatically performed only when 64-byte data is sent. This processing is not performed automatically when data less than 64 bytes is sent. (b) EP2i DMA Transfer Procedure 1. Set bits EP2iT1 and EP2iT0 in UDMAR. 2. DMAC settings (in DMAC specify number of transfers for 150 bytes). 3. Start DMAC. 4. DMA transfer. 5.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) This kind of internal processing is performed when the currently selected data FIFO becomes empty. Accordingly, this processing is automatically performed both when 64-byte data is sent and when data less than 64 bytes is sent. (b) EP2o DMA Transfer Procedure The DMAC transfer unit should be one packet.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.6.2 DMA Transfer by Auto-Request (1) Overview Burst mode transfer or ycle steal transfer can be selected for the on-chip DMAC auto-request transfer. Endpoints that can be transferred by the on-chip DMAC are all registers (UEDR0s, UEDR0i, UEDR0o, UEDR1i, UEDR2i, UEDR2o, UEDR3i, UEDR3o, UEDR4i, UEDR4o, and UEDR5i). Confirm flags and interrupts corresponding to each data register before activating the DMA.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 64 bytes 64 bytes Write 1 to EP2iPKTE 22 bytes Write 1 to EP2iPKTE Write 1 to EP2iPKTE Figure 15.27 EP2iPKTE Operation in UTRG0 (Auto-Request) (4) EPno DMA Transfer (n = 0, 2, 4) (a) EPnoRDFN Bits of UTRG (n = 0, 2, 4) Note that 1 is not automatically written to EPnoRDFN in case of auto-request transfer. Always write 1 to EPnoRDFN by the CPU. The following example shows when EP2o receives 150-byte data from the host.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.7 Endpoint Configuration Example Figure 15.29 shows an example of endpoint configuration. EPINFO data for the endpoint configuration shown in figure 15.29 is shown in table 15.9. In this example, two endpoints are not used. However, note that to load all EPINFO data from UEP1R00_0 to UEPIR22_4, dummy data must be written to the unused endpoints. An example of dummy data is also shown in table 15.9.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Table 15.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Table 15.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Table 15.9 EPINFO Data Settings EPINFO Data Settings Based on Bluetooth Standard Register No.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) EPINFO Data Settings Based on Bluetooth Standard Register No.
H8S/2215 Group 15.8 Section 15 Universal Serial Bus Interface (USB) USB External Circuit Example Figures 15.30 and 15.31 show the USB external circuit examples when the on-chip transceiver is used. Figures 15.32 and 15.33 show the USB external circuit examples when an external transceiver is used. USB Internal transceiver *3 Pxx VCC *4 DrVCC (P36) (3.3 V) VBUS (3.3 V) USD+ VCC (3.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) USB Internal transceiver *3 Pxx VCC *2 *4 DrVCC (P36)(3.3 V) IRQx VBUS (3.3 V) USD+ USD- DrVSS VSS UBPM VCC VCC 3.3 V 24 Ω 24 Ω 1: Self-powered mode *1 VCC *1 1.5 kΩ Pull-up control external circuit for full speed VBUS D+ (5 V) D- GND USB connector Notes: 1. To protect the LSI, voltage applicable IC such as HD74LV-A series must be used even when the system power is turned off. 2.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) P17 SUSPND PA3 SPEED P15 DrVSS VSS UBPM VCC OE P13 FSE0 VPO VM RCV VP P12 P11 *3 Pxx VCC *4 DrVCC (P36) (3.3 V) VBUS (3.3 V) P10 USB D- MODE D+ GND VCC External transceiver (ISP1104 manufactured by NXP) VCC (3.3 V) Regulator *1 Rs 0: Bus-powered mode Rs VCC D+ *2 1.5 kΩ Pull-up control external circuit for full speed DGND VBUS (5 V) USB connector Notes: 1. Step-down to the operating voltage VCC (3.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) P17 SUSPND PA3 SPEED P15 DrVSS VSS UBPM VCC OE P13 FSE0 P10 VPO VM RCV VP *3 Pxx VCC *2 *4 DrVCC (P36)(3.3 V) IRQx VBUS (3.3 V) P12 P11 USB *1 D- Rs MODE D+ GND VCC VCC 3.3 V External transceiver (ISP1104 manufactured by NXP) VCC 1: Self-powered mode Rs VCC *1 1.5 kΩ Pull-up control external circuit for full speed D+ D- VBUS (5 V) GND USB connector Notes: 1.
H8S/2215 Group 15.9 Usage Notes 15.9.1 Operating Frequency Section 15 Universal Serial Bus Interface (USB) • In H8S/2215 When the on-chip PLL circuit is used, the system clock of this LSI must be 16 MHz. This 16MHz system clock, used as base clock, is tripled in the on-chip PLL circuit to generate the 48MHz USB operating clock. When the USB operating clock (48 MHz) oscillator or 48-MHz external clock is used, the system clock of the LSI must be 13-MHz to 16-MHz.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.9.4 FIFO Clear If the USB cable is disconnected during communication, old data may be contained in the FIFO. Accordingly, FIFO must be cleared immediately after USB cable connection. In addition, after bus reset, all FIFO must also be cleared. Note, however, that FIFOs that are currently used for data transfer to or from the host must not be cleared. 15.9.
H8S/2215 Group 15.9.7 Section 15 Universal Serial Bus Interface (USB) EP3o Isochronous Transfer • Reception of EP3o data larger than the maximum packet size The EP3o data FIFO cannot receive data with size larger than the maximum packet size; the excessive data is lost. In this case, the receive size register 3o (UESZ3o) can count up to the maximum packet size and the EP3o abnormal transfer flag (EP3oTF) is set to 1. Figure 15.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) • EP3o receive data and status bit reading As shown in figure 15.35, FIFO are switched on SOF packet reception. FIFOs thus store the latest data. Accordingly, receive data sent from the host in frame [N] can only be read in frame [N+1]. In addition, the EP3oTF and EP3oTS status bits of UIFR1 are automatically switched on with each SOF packet reception; the EP3oTF and EP3oTS status in frame [N] can only be read in frame [N + 1].
H8S/2215 Group 15.9.8 Section 15 Universal Serial Bus Interface (USB) Reset • A manual reset should not be performed during USB communication as the LSI will stop with the USD+, USD- pin state maintained. This USB module uses synchronous reset for some registers. The reset state of these registers must be cancelled after the clock oscillation stabilization time has passed. At initialization, reset must be cancelled using the following procedure: 1.
Section 15 Universal Serial Bus Interface (USB) H8S/2215 Group 15.9.10 Level Shifter for VBUS and IRQx Pins The VBUS and IRQx pins of this USB module must be connected to the USB connector’s VBUS pin via a level shifter. This is because the USB module has a circuit that operates by detecting USB cable connection or disconnection.
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) Procedure to enter software standby mode (1) Specify IRQ6 to falling edge sensitive (Set IRQ6E in IER to 1) (Write IRQ6SCB and A in ISCRH to 01) (2) Detect USB bus suspend state USPND pin = High (3) IRQ6 = Low (falling edge output) Set IRQ6F in ISR to 1 Set SPRSi and SPRSs in UIFR3 to 1 (4) Confirm SPRSs in UIFR3 as 1 Clear IRQ6E in IER to 0* Clear SPRSi in UIFR3 to 0 Clear SFME in UCTLR to 0 Procedure to cancel software standby mode
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) (1) USB bus state Normal (10) (2) USPND IRQ6 (23) SOF Resume → Normal Suspend (10) (3) (5) (11) ISR/IRQ6F (3) (4) (11) UIFR3/SPRSi (3) (4) (18) (19) UIFR3/SPRSs (3) (4) (18) (19) (20) (14) UIFR3/SOF (24) UCTLR/SFME (4) USB module stop (6) Standby mode (25) (15) (8) (12) System clock (16 MHz) (9) φ (16 MHz) (9) USB internal clock (16 MHz) (13) (14) (7) (16) UIFR3/ CK48READY (21) CLK48 (48 MHz) (7)
H8S/2215 Group Section 15 Universal Serial Bus Interface (USB) 15.9.14 Pin Processing when USB Not Used Pin processing should be performed as follows. DrVCC = Vcc, DrVSS = 0 V, USD+ = USD- = USPND = open state, VBUS = UBPM = 0 V 15.9.
Section 15 Universal Serial Bus Interface (USB) H8S/2215 Group 15.9.17 Notes on UIFRO The bit-clear instruction cannot be used to clear a flag in some USB interrupt flag registers to 0. These registers have flags which are cleared to 0 by writing 0 and to which writing 1 is ignored. The concerning registers are USB interrupt flag registers 0 to 3 (UIFR0 to UIFR3) in the H8S/2215 Group.
H8S/2215 Group Section 16 A/D Converter Section 16 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to six analog input channels to be selected. The block diagram of the A/D converter is shown in figure 16.1. 16.1 Features • 10-bit resolution • Six input channels • Conversion time: 8.1 µs per channel (at 16-MHz operation), 10.7 µs per channel (at 24-MHz operation)* Note: * Available only in H8S/2215R, H8S/2215T and H8S/2215C.
H8S/2215 Group Section 16 A/D Converter AVCC Module data bus Bus interface Successive approximation register 10 bit D/A Vref Internal data bus A D D R A A D D R B A D D R C A D D R D A D C S R A D C R + AN0 AN2 AN3 AN14 AN15 φ/2 Multiplexer AN1 Comparator Control circuit Sample and hold circuit φ/4 φ/8 φ/16 ADI interrupt signal Time conversion start trigger from TPU or 8 bit timer ADTRG Off during A/D conversion standby On during A/D conversion AVSS Legend: ADCR: ADCSR: ADDRA: ADDRB:
H8S/2215 Group 16.2 Section 16 A/D Converter Input/Output Pins Table 16.1 summarizes the input pins used by the A/D converter. The AN0 to AN3 and AN14 to AN15 pins are analog input pins. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the reference voltage pin for the A/D conversion. Table 16.
H8S/2215 Group Section 16 A/D Converter 16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 16.2. The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0. The data bus between the CPU and the A/D converter is 8 bits wide.
H8S/2215 Group Section 16 A/D Converter Bit Bit Name Initial Value R/W Description 6 ADIE 0 R/W A/D Interrupt Enable A/D conversion end interrupt (ADI) request enabled when 1 is set. 5 ADST 0 R/W A/D Start Clearing this bit to 0 stops A/D conversion, and the A/D converter enters the unit state. Setting this bit to 1 starts A/D conversion. It can be set to 1 by software, the timer conversion start trigger, and the A/D external trigger (ADTRG).
H8S/2215 Group Section 16 A/D Converter 16.3.3 A/D Control Register (ADCR) The ADCR enables A/D conversion started by an external trigger signal. Bit Bit Name Initial Value R/W Description 7 TRGS1 0 R/W Timer Trigger Select 1 and 0 6 TRGS0 0 R/W Enables the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped (ADST = 0).
H8S/2215 Group 16.4 Section 16 A/D Converter Interface to Bus Master ADDRA to ADDRD are 16-bit registers. As the data bus to the bus master is 8 bits wide, the bus master accesses to the upper byte of the registers directly while to the lower byte of the registers via the temporary register (TEMP). Data in ADDR is read in the following way: When the upper-byte data is read, the upper-byte data will be transferred to the CPU and the lower-byte data will be transferred to TEMP.
Section 16 A/D Converter 16.5 H8S/2215 Group Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 16.5.
H8S/2215 Group Section 16 A/D Converter Set* ADIE ADST A/D conversion starts Set* Set* Clear* Clear* ADF State of channel 0 (AN0) Idle State of channel 1 (AN1) Idle State of channel 2 (AN2) Idle State of channel 3 (AN3) Idle A/D conversion 1 Idle A/D conversion 2 Idle ADDRA ADDRB Read conversion result* A/D conversion result 1 Read conversion result* A/D conversion result 2 ADDRC ADDRD Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 16.
H8S/2215 Group Section 16 A/D Converter Continuous A/D conversion execution Clear*1 Set*1 ADST Clear*1 ADF A/D conversion time State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) Idle Idle A/D conversion 1 Idle Idle A/D conversion 2 Idle Idle A/D conversion 4 A/D conversion 5 *2 Idle A/D conversion 3 State of channel 3 (AN3) Idle Idle Transfer ADDRA A/D conversion result 1 ADDRB ADDRC A/D conversion result 4 A/D conversion result 2 A/D conversion result 3 ADDR
H8S/2215 Group Section 16 A/D Converter (1) φ Address (2) Write signal Input sampling timing ADF tD tSPL tCONV Legend: (1): ADCSR write cycle (2): ADCSR address tD: A/D conversion start delay tSPL: Input sampling time tCONV: A/D conversion time Figure 16.5 A/D Conversion Timing Table 16.
H8S/2215 Group Section 16 A/D Converter Table 16.4 A/D Conversion Time (Scan Mode) CKS1 CKS0 Conversion Time (State) 0 0 512 (Fixed) 1 256 (Fixed) 0 128 (Fixed) 1 64 (Fixed) 1 16.5.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS0 and TRGS1 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion.
H8S/2215 Group 16.6 Section 16 A/D Converter Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 enables ADI interrupt requests while the bit ADF in ADCSR is set to 1 after A/D conversion is completed. The DMAC or DTC can be activated by an ADI interrupt. Table 16.5 A/D Converter Interrupt Source Name Interrupt Source Interrupt Source Flag DMAC or DTC Activation ADI A/D conversion completed ADF Possible 16.
H8S/2215 Group Section 16 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 16.7 A/D Conversion Precision Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 16.
H8S/2215 Group Section 16 A/D Converter 16.8 Usage Notes 16.8.1 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion precision is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less.
H8S/2215 Group Section 16 A/D Converter 16.8.3 Range of Analog Power Supply and Other Pin Settings If the conditions below are not met, the reliability of the device may be adversely affected. • Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVSS ≤ ANn ≤ Vref. • Relationship between AVcc, AVss and Vcc, Vss Set AVss = Vss as the relationship between AVcc, AVss and Vcc, Vss.
H8S/2215 Group Section 16 A/D Converter AVCC Vref *1 100 Ω Rin*2 *1 AN0 to AN11 0.1 μF AVSS Notes: Values are reference values. 1. 10 μF 0.01 μF 2. Rin: Input impedance Figure 16.10 Example of Analog Input Protection Circuit Table 16.6 Analog Pin Specifications Item Min Max Unit Analog input capacitance — 20 pF — 5* kΩ Permissible signal source impedance Note: * Vcc = 2.7 to 3.6 V 10 kΩ ANn To A/D converter 20 pF Note: Values are reference values. Figure 16.
Section 16 A/D Converter 16.8.6 H8S/2215 Group Module Stop Mode Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 22, Power-Down Modes. Page 618 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 17 D/A Converter Section 17 D/A Converter This LSI includes a D/A converter with 2 channels. 17.1 Features D/A converter features are listed below. • 8-bit resolution • Two output channels • Maximum conversion time of 10 µs (with 20 pF load) • Output voltage of 0 V to Vref • D/A output hold function in software standby mode • Module stop mode can be set Figure 17.1 shows a block diagram of the D/A converter.
H8S/2215 Group Section 17 D/A Converter 17.2 Input/Output Pins Table 17.1 summarizes the input and output pins of the D/A converter. Table 17.1 Pin Configuration Pin Name Symbol I/O Function Analog power pin AVCC Input Analog power Analog ground pin AVSS Input Analog ground and reference voltage Analog output pin 0 DA0 Output Channel 0 analog output Analog output pin 1 DA1 Output Channel 1 analog output Reference voltage pin Vref Input Analog reference voltage 17.
H8S/2215 Group 17.3.2 Section 17 D/A Converter D/A Control Register (DACR) DACR controls the operation of the D/A converter. DACR01 Bit Bit Name Initial Value R/W Description 7 DAOE1 0 R/W D/A Output Enable 1 6 DAOE0 0 R/W D/A Output Enable 0 5 DAE 0 R/W D/A Enable Control the D/A conversion and analog output.
H8S/2215 Group Section 17 D/A Converter [1] Write the conversion data to DADR_0. [2] Set the DAOE0 bit in DACR01 to 1. D/A conversion is started. The conversion result is output after the conversion time tDCONV has elapsed. The output value is expressed by the following formula: DADR contents ——————— × Vref 256 The conversion results are output continuously until DADR_0 is written to again or the DAOE0 bit is cleared to 0. [3] If DADR_0 is written to again, the conversion is immediately started.
H8S/2215 Group 17.5 Usage Note 17.5.1 Module Stop Mode Setting Section 17 D/A Converter Operation of the D/A converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the D/A converter to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 22, Power-Down Modes. REJ09B0140-0900 Rev. 9.
Section 17 D/A Converter Page 624 of 846 H8S/2215 Group REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 18 RAM Section 18 RAM This LSI has on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer. The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR). For details on SYSCR, refer to section 3.2.2, System Control Register (SYSCR).
Section 18 RAM Page 626 of 846 H8S/2215 Group REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) Section 19 Flash Memory (F-ZTAT Version) The features of the on-chip flash memory are summarized below. The block diagram of the flash memory is shown in figure 19.1. 19.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) • Flash memory emulation in RAM ⎯ Flash memory programming can be emulated in real time by overlapping a part of RAM onto flash memory.
H8S/2215 Group 19.2 Section 19 Flash Memory (F-ZTAT Version) Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, this LSI enters an operating mode as shown in figure 19.2. In user mode, flash memory can be read but not programmed or erased. The boot and user program modes are provided as modes to write and erase the flash memory. The differences between boot mode and user program mode are shown in table 19.1.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) Table 19.1 Differences between Boot Mode and User Program Mode SCI,USB Boot Mode User Program Mode User Mode Total erase Yes Yes No Block erase No Yes No Programming control program* Program/program-verify Erase/erase-verify — Program/program-verify Emulation Note: * To be provided by the user, in accordance with the recommended algorithm. Page 630 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in this LSI (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI or USB communication.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) 1. Initial state The FWE assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. 2.
H8S/2215 Group 19.3 Section 19 Flash Memory (F-ZTAT Version) Block Configuration Figure 19.5 shows the block configuration of 256-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 4 kbytes (eight blocks), 32 kbytes (one block), and 64 kbytes (three blocks). Erasing is performed in these divided units.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) 19.4 Input/Output Pins The flash memory is controlled by means of the pins shown in table 19.2. Table 19.
H8S/2215 Group 19.5.1 Section 19 Flash Memory (F-ZTAT Version) Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory transit to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 19.8, Flash Memory Programming/Erasing. Bit 7 Bit Name Initial Value FWE —* R/W Description R Flash Write Enable Reflects the input level at the FWE pin.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) Bit Bit Name Initial Value R/W Description 2 PV1 R/W Program-Verify 0 When this bit is set to 1, the flash memory transits to program-verify mode. When it is cleared to 0, programverify mode is cancelled. [Setting condition] • 1 E1 0 R/W When FWE = 1 and SWE1 = 1 Erase When this bit is set to 1 while the SWE1 and ESU1 bits are 1, the flash memory transits to erase mode. When it is cleared to 0, erase mode is cancelled.
H8S/2215 Group 19.5.3 Section 19 Flash Memory (F-ZTAT Version) Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 and EBR2 to be automatically cleared to 0. Bit Bit Name Initial Value R/W Description 7 EB7 0 R/W When this bit is set to 1, 4 kbytes of EB7 (H'007000 to H'007FFF) are to be erased.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) 19.5.4 Erase Block Register 2 (EBR2) EBR2 specifies the flash memory erase area block. EBR2 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 and EBR2 to be automatically cleared to 0. Bit Bit Name Initial Value 7 to 4 — All 0 R/W R/W Description Reserved The write value should always be 0.
H8S/2215 Group 19.5.5 Section 19 Flash Memory (F-ZTAT Version) RAM Emulation Register (RAMER) RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER settings should be made in user mode or user program mode. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) 19.5.6 Serial Control Register X (SCRX) SCRX performs register access control. Bit Bit Name Initial Value 7 to 4 — All 0 R/W Description R/W Reserved The write value should always be 0. 3 FLSHE 0 R/W Flash Memory Control Register Enable Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Setting the FLSHE bit to 1 enables read/write access to the flash memory control registers.
H8S/2215 Group 19.6 Section 19 Flash Memory (F-ZTAT Version) On-Board Programming Modes When pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 19.3.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) H8S/2215 Group 1 01× Host Write data reception Verify data transmission FWE* MD2 to 0* RxD2 SCI_2 TxD2 Flash memory On-chip RAM Legend: ×: Don’t care Note: * FWE pin and mode pin input must satisfy the mode programming setup time (tMDS = 200 ns) when a reset is released. Figure 19.6 System Configuration in SCI Boot Mode Table 19.4 shows the boot mode operations between reset end and branching to the programming control program. 1.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) performed normally, initiate boot mode again by a reset. Depending on the host’s transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and the chip. To operate the SCI properly, set the host’s transfer bit rate and system clock frequency of this LSI within the ranges listed in table 19.5. 5. In boot mode, a part of the on-chip RAM area (4 kbytes) is used by the boot program.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) Table 19.4 SCI Boot Mode Operation Item Host Operation LSI Operation Branches to boot program at resetstart. Bit rate adjustment Continuously transmits data H'00 at specified bit rate. Measures low-level period of receive data H'00. Calculates bit rate and sets it in BRR of SCI_2. Transmits data H'55 when data H'00 is received error-free. Transmits data H'00 to host as adjustment end indication.
H8S/2215 Group 19.6.2 Section 19 Flash Memory (F-ZTAT Version) USB Boot Mode (HD64F2215U, HD64F2215RU, HD64F2215TU and HD64F2215CU) • Features ⎯ Selection of bus-powered mode or self-powered mode ⎯ HD64F2215U: Supports only 16-MHz system clock, with USB operating clock generation by means of PLL3 multiplication HD64F2215RU, HD64F2215TU and HD64F2215CU: Supports either 16-MHz or 24-MHz system clock, with USB operating clock generation by means of PLL2 or PLL3 multiplication, respectively.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) • Overview When a reset start is performed after the pins of this LSI have been set to boot mode, a boot program incorporated in the microcomputer beforehand is activated, and the prepared programming control program is transmitted sequentially to the host using the USB. With this LSI, the programming control program received by the USB is written to a programming control program area in on-chip RAM.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) 2. When the boot program is activated, enumeration with respect to the host is carried out. Enumeration information is shown in table 19.6. When enumeration is completed, transmit a single H'55 byte from the host. If reception has not been performed normally, restart boot mode by means of a reset. 3. Set the frequency for transmission from the host as a numeric value in units of MHz × 100 (ex: 16.00 MHZ → H'0640). 4.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) Table 19.
H8S/2215 Group 19.6.3 Section 19 Flash Memory (F-ZTAT Version) Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) 19.7 Flash Memory Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. Emulation can be performed in user mode or user program mode. Figure 19.9 shows an example of emulation of real-time flash memory programming. 1.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) Example in which flash memory block area EB0 is overlapped is shown in figure 19.10. 1. The RAM area to be overlapped is fixed at a 4-kbyte area in the range of H'FFD000 to H'FFDFFF. 2. The flash memory area to overlap is selected by RAMER from a 4-kbyte area among one of the EB0 to EB7 blocks. 3. The overlapped RAM area can be accessed from both the flash memory addresses and RAM addresses. 4.
Section 19 Flash Memory (F-ZTAT Version) 19.8 H8S/2215 Group Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: program mode, erase mode, program-verify mode, and erase-verify mode.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) Write pulse application subroutine Start of programming Subroutine Write Pulse START WDT enable Set SWE1 bit in FLMCR1 Set PSU1 bit in FLMCR1 Wait (y) µs *6 Wait (x) µs *6 Store 128-byte program data in program data area and reprogram data area *4 n=1 Start of programming Set P1 bit in FLMCR1 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) 19.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 19.12 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register 1 (EBR1), and erase block register 2 (EBR2). To erase multiple blocks, each block must be erased in turn. 3.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) Start *1 Set SWE1 bit in FLMCR1 Wait (x) μs *2 n=1 Set EBR1 (2) *4 Enable WDT Set ESU1 bit in FLMCR1 Wait (y) μs *2 Set E1 bit in FLMCR1 Wait (z) μs *2 Clear E1 bit in FLMCR1 Wait (a) μs *2 Clear ESU1 bit in FLMCR1 Wait (b) μs *2 Disable WDT Clear EV1 bit in FLMCR1 Wait (g) μs *2 Set block start address as verify address H'FF dummy write to verify address Wait (e) μs *2 Read verify data *3 Verify data = all 1s? Increment addres
Section 19 Flash Memory (F-ZTAT Version) 19.9 H8S/2215 Group Program/Erase Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.9.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset or standby mode.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) The FLMCR1, FLMCR2, EBR1 and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be reentered by re-setting the P1 or E1 bit. However, PV1 and EV1 bit setting is enabled, and a transition can be made to verify mode. 19.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) MCU mode Programmer mode H'000000 H'00000 On-chip ROM space 256 kbytes H'03FFFF H'3FFFF Figure 19.13 Memory Map in Programmer Mode 19.12 Power-Down States for Flash Memory In user mode, the flash memory will operate in either of the following states: • Normal operating mode The flash memory can be read and written to. • Standby mode All flash memory circuits are halted. Table 19.
H8S/2215 Group 19.13 Section 19 Flash Memory (F-ZTAT Version) Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode, the RAM emulation function, and PROM mode are summarized below. • Use the specified voltages and timing for programming and erasing. Applied voltages in excess of the rating can permanently damage the device.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) • Use the recommended algorithm when programming and erasing flash memory. The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P1 or E1 bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. • Do not set or clear the SWE1 bit during execution of a program in flash memory.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) Wait time: x Programming/ erasing possible Wait time: θ φ min 0 μs tOSC1 VCC tMDS*3 FWE min 0 μs MD2, MD1*1 tMDS*3 RES SWE1 set SWE1 cleared SWE1 bit Period during which flash memory access is prohibited x: Wait time after setting SWE1 bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) Wait time: x Programming/ erasing Wait time: θ possible φ min 0 μs tOSC1 VCC FWE MD2, MD1*1 tMDS*3 RES SWE1 set SWE1 cleared SWE1 bit Period during which flash memory access is prohibited (x: Wait time after setting SWE1 bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
H8S/2215 Group *4 *4 Programming/ erasing possible Wait time: x Wait time: x Programming/ erasing possible Wait time: x Programming/ erasing possible Programming/ erasing possible Wait time: x Section 19 Flash Memory (F-ZTAT Version) *4 *4 φ tOSC1 VCC min 0ms FWE 2 tMDS* tMDS MD2, MD1 tMDS tRESW RES SWE1 cleared SWE1 set SWE1 bit Mode change*1 Boot mode Mode User change*1 mode User program mode User mode User program mode Period during which flash memory access is prohibited (x: Wait ti
H8S/2215 Group Section 19 Flash Memory (F-ZTAT Version) 19.14 Note on Switching from F-ZTAT Version to Masked ROM Version The masked ROM version does not have the internal registers for flash memory control that are provided in the F-ZTAT version. Table 19.7 lists the registers that are present in the F-ZTAT version but not in the masked ROM version. If a register listed in table 19.7 is read in the masked ROM version, an undefined value will be returned.
H8S/2215 Group Section 20 Masked ROM Section 20 Masked ROM This LSI incorporates a masked ROM which has the following features. 20.1 Features • Size: Product Class H8S/2215 Group ROM Size ROM Address (Modes 6 and 7) HD6432215B 128 kbytes H'000000 to H'01FFFF HD6432215C 64 kbytes H'000000 to H'00FFFF • Connected to the bus master through 16-bit data bus, enabling one-state access to both byte data and word data. Figure 20.1 shows a block diagram of the on-chip masked ROM.
Section 20 Masked ROM Page 666 of 846 H8S/2215 Group REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 21 Clock Pulse Generator Section 21 Clock Pulse Generator This LSI has an on-chip clock pulse generator that generates the system clock (φ), the bus master clock, and internal clocks. The clock pulse generator consists of a system clock oscillator, duty adjustment circuit, medium-speed clock divider, bus master clock selection circuit, USB operating clock oscillator, PLL (Phase Locked Loop) circuit, and USB operating clock selection circuit.
Section 21 Clock Pulse Generator H8S/2215 Group The frequency of the system clock oscillator can be changed by software by means of settings in the low-power control register (LPWRCR) and system clock control register (SCKCR). Either USB operating clock (48 MHz) oscillator or PLL 48-MHz clock can be selected by software by means of setting the USB control register (UCTLR). For details, refer to section 15, Universal Serial Bus Interface (USB). 21.
H8S/2215 Group Section 21 Clock Pulse Generator Bit Bit Name Initial Value R/W Description 7 PSTOP φ Clock Output Disable 0 R/W Controls φ output. Operation differs depending on the mode. For details, see section 22.7, φ Clock Output Disabling Function. 0: φ output, fixed high, or high impedance 1: Fixed high or high impedance 6 — 0 R/W Reserved This bit can be read from or written to, but the write value should always 0. 5, 4 — All 0 — Reserved These bits are always read as 0.
H8S/2215 Group Section 21 Clock Pulse Generator 21.1.2 Low-Power Control Register (LPWRCR) LPWRCR selects whether the oscillator’s built-in feedback resistor and duty adjustment circuit are used with external clock input. Bit Bit Name Initial Value R/W Description 7 to 4 — Reserved 3 RFCUT All 0 R/W These bits can be read from or written to, but the write value should always be 0.
H8S/2215 Group 21.2 Section 21 Clock Pulse Generator System Clock Oscillator The system clock can be supplied by connecting a crystal or ceramic resonator, or by input of an external clock. Suitable resonators differ depending on the product. For details, see table 21.1. Table 21.
H8S/2215 Group Section 21 Clock Pulse Generator CL XTAL L Rs C0 EXTAL AT-cut parallel-resonance type Figure 21.3 Crystal Resonator Equivalent Circuit Table 21.3 Crystal Resonator Characteristics Frequency (MHz) 13 16 24* RS max (Ω) 60 50 40 C0 max (pF) 7 7 Note: 21.2.2 Available only in H8S/2215R and H8S/2215C. * Connecting a Ceramic Resonator (H8S/2215T) Figure 21.6 shows an example wiring diagram for connecting a ceramic resonator.
H8S/2215 Group Section 21 Clock Pulse Generator External clock input EXTAL Open XTAL (a) XTAL pin left open External clock input EXTAL XTAL (b) Complementary clock input at XTAL pin Figure 21.5 External Clock Input (Examples) Table 21.4 shows the input conditions for the external clock. Table 21.4 External Clock Input Conditions VCC = 2.7 V to 3.6 V Symbol Min Item VCC = 3.0 V to 3.6 V* Test Max Min Max Unit Conditions External clock input low tEXL pulse width 25 — 15.
H8S/2215 Group Section 21 Clock Pulse Generator and tEXr = tEXf = 6.25 ns, the maximum operating frequency becomes 13.3 MHz depending on the clcok cycle time of 75 ns. Table 21.5 External Clock Input Conditions when Duty Adjustment Circuit Is Not Used VCC = 2.7 V to 3.6 V Item Symbol Min VCC = 3.0 V to 3.6 V* Test Max Min Max Unit Conditions External clock input low tEXL pulse width 31.25 — 20.8 — ns External clock input high tEXH pulse width 31.25 — 20.
H8S/2215 Group 21.6 Section 21 Clock Pulse Generator USB Operating Clock (48 MHz) USB operating clock can be supplied by connecting a ceramic resonator, or by input of an external clock. 21.6.1 Connecting a Ceramic Resonator Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 21.7. Ceramic resonator: CSTCW48M0X11∗∗∗-R0 EXTAL48 (Murata Manufacturing Co.,Ltd.
H8S/2215 Group Section 21 Clock Pulse Generator Table 21.6 shows the input conditions for the 48-MHz external clock. Table 21.6 External Clock Input Conditions when Duty Adjustment Circuit Is Not Used Item Symbol Min Max Unit Test Conditions External clock frequency (48 MHz) tFREQ 47.88 48.12 MHz Figure 21.10 Clock rise time tR48 — 5 ns Clock fall time tF48 — 5 ns Duty (tHIGH/tFREQ) tDUTY 40 60 % tFREQ tHIGH tLOW 90% VCC × 0.5 EXTAL48 10% tR48 tF48 Figure 21.
H8S/2215 Group 21.7 Section 21 Clock Pulse Generator PLL Circuit for USB The PLL circuit has the function of tripling or doubling* the 16- or 24-MHz* clock from the system oscillator to generate the 48-MHz USB operating clock. When the PLL circuit is used, set the UCKS3 to UCKS0 bits of UCTLR. For details, refer to section 15, Universal Serial Bus Interface (USB). When the PLL circuit is not used, connect the PLLVCC pin to VCC, and leave the PLLCAP pin open as shown in figure 21.11.
H8S/2215 Group Section 21 Clock Pulse Generator 21.8 Usage Notes 21.8.1 Note on Crystal Resonator Since various characteristics related to the crystal resonator are closely linked to the user’s board design, thorough evaluation is necessary on the user’s part, using the resonator connection examples shown in this section as a guide.
H8S/2215 Group Section 21 Clock Pulse Generator H8S/2215 Group Request switchover of external clock Ouptut port Interrupted external signal Control cycle External clock 1 External clock 2 Selector External clock switchover signal External interrupt EXTAL Figure 21.
Section 21 Clock Pulse Generator Page 680 of 846 H8S/2215 Group REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 22 Power-Down Modes Section 22 Power-Down Modes In addition to the normal program execution state, this LSI has five power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on.
H8S/2215 Group Section 22 Power-Down Modes Table 22.
H8S/2215 Group Section 22 Power-Down Modes Program-halted state Reset Execution state STBY pin = Low Manual reset state Reset state Hardware standby mode STBY pin = High RES pin = Low RES pin = High SSBY = 0 Program execution state Sleep mode (main clock) SLEEP command High-speed mode (main clock) Any interrupt SCK2 to SCK0 = 0 SLEEP command SCK2 to SCK0 ≠ 0 SSBY = 1 Software standby mode External interrupt* Medium-speed mode (main clock) USB suspend/resume interrupt : Transition after ex
H8S/2215 Group Section 22 Power-Down Modes 22.1 Register Descriptions The registers relating to the power down mode are shown below. For details on the system clock control register (SCKCR), refer to section 21.1.1, System Clock Control Register (SCKCR). • Standby control register (SBYCR) • System clock control register (SCKCR) • Module stop control register A (MSTPCRA) • Module stop control register B (MSTPCRB) • Module stop control register C (MSTPCRC) 22.1.
H8S/2215 Group Section 22 Power-Down Modes Bit Bit Name Initial Value R/W Description 6 STS2 0 R/W Standby Timer Select 2 to 0 5 STS1 0 R/W 4 STS0 0 R/W These bits select the MCU wait time for clock stabilization when cancel software standby mode by an external interrupt. With a crystal oscillator (tables 22.3 and 22.4), select a wait time of tOSC2 ms (oscillation stabilization time) or more, depending on the operating frequency.
H8S/2215 Group Section 22 Power-Down Modes 22.1.2 Module Stop Control Registers A to C (MSTPCRA to MSTPCRC) MSTPCR, comprising three 8-bit readable/writable registers, performs module stop mode control. Setting a bit to 1, causes the corresponding module to enter module stop mode, while clearing the bit to 0 clears the module stop mode.
H8S/2215 Group Section 22 Power-Down Modes MSTPCRC Bit Bit Name Initial Value R/W Module 7 MSTPC7* MSTPC6* 1 R/W — 1 R/W — 1 R/W D/A converter 4 MSTPC5 MSTPC4* 1 R/W — 3 MSTPC3* 1 R/W — 2 1 R/W — 1 MSTPC2* MSTPC1* 1 R/W — 0 MSTPC0* 1 R/W — 6 5 Note: * MSTPA3, MSTPA2, MSTPA0, MSTPB4 to MSTPB1, MSTPC7, MSTPC6, MSTPC4 to MSTPC0 are readable/writable bits with an initial value of 1 and should always be written with 1. REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 22 Power-Down Modes 22.2 Medium-Speed Mode When the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to mediumspeed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (DTC or DMAC) also operate in medium-speed mode.
H8S/2215 Group Section 22 Power-Down Modes Medium-speed mode φ, supporting module clock Bus master clock Internal address bus SCKCR SCKCR Internal write signal Figure 22.2 Medium-Speed Mode Transition and Clearance Timing 22.3 Sleep Mode 22.3.1 Transition to Sleep Mode When the SLEEP instruction is executed when the SSBY bit in SBYCR is 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers are retained.
Section 22 Power-Down Modes 22.4 Software Standby Mode 22.4.1 Transition to Software Standby Mode H8S/2215 Group A transition is made to software standby mode when the SLEEP instruction is executed when the SSBY bit in SBYCR is 1. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than the A/D converter, and the states of I/O ports, are retained.
H8S/2215 Group 22.4.3 Section 22 Power-Down Modes Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. • Using a Crystal Oscillator Set bits STS2 to STS0 so that the standby time is at least tOSC2 ms (the oscillation stabilization time). Table 22.3 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. • Using an External Clock Set bits STS2 to STS0 as any value.
H8S/2215 Group Section 22 Power-Down Modes 22.4.4 Software Standby Mode Application Example Figure 22.3 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin.
H8S/2215 Group 22.5 Hardware Standby Mode 22.5.1 Transition to Hardware Standby Mode Section 22 Power-Down Modes When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state.
H8S/2215 Group Section 22 Power-Down Modes 22.5.3 Hardware Standby Mode Timing Figure 22.4 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation stabilization time, then changing the RES pin from low to high.
H8S/2215 Group 22.5.4 Section 22 Power-Down Modes Hardware Standby Mode Timings Timing of Transition to Hardware Standby Mode 1. To retain RAM contents with the RAME bit set to 1 in SYSCR Drive the RES signal low at least 10 states before the STBY signal goes low, as shown in figure 22.5. After STBY has gone low, RES has to wait for at least 0 ns before becoming high. STBY t1 ≥ 10 tcyc t2 ≥ 0 ns RES Figure 22.5 Timing of Transition to Hardware Standby Mode 2.
H8S/2215 Group Section 22 Power-Down Modes 22.6 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle.
H8S/2215 Group 22.8 Usage Notes 22.8.1 I/O Port Status Section 22 Power-Down Modes In software standby mode, I/O port states are retained. In addition, if the OPE bit is set to 1, the address bus and bus control signal output are retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. 22.8.
Section 22 Power-Down Modes Page 698 of 846 H8S/2215 Group REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 23 List of Registers Section 23 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register Addresses (address order) • Registers are listed from the lower allocation addresses. • Registers are classified by functional modules. • The access size is indicated. 2.
H8S/2215 Group Section 23 List of Registers Number of Bits Address Data Bus Number of Width Access States Module UEPIR00_0 to UEPIR22_4 8 H'C00000 to H'C00072 8 3 USB USB control register UCTLR 8 H'C00080 8 3 USB test register A UTSTRA 8 H'C00081 8 3 USB DMAC transfer request register UDMAR 8 H'C00082 8 3 USB device resume register UDRR 8 H'C00083 8 3 USB trigger register 0 UTRG0 8 H'C00084 8 3 Register Name Abbreviation USB end point information register 00_0 to 2
H8S/2215 Group Section 23 List of Registers Number of Bits Address Data Bus Number of Width Access States Module USB endpoint receive data size register 0o UESZ0o 8 H'C000BC 8 3 USB USB endpoint receive data size register 2o UESZ2o 8 H'C000BD 8 3 USB endpoint receive data size register 3o UESZ3o 8 H'C000BE 8 3 USB endpoint receive data size register 4o UESZ4o 8 H'C000BF 8 3 USB interrupt flag register 0 UIFR0 8 H'C000C0 8 3 USB interrupt flag register 1 UIFR1 8 H'C000C1 8
H8S/2215 Group Section 23 List of Registers Register Name Abbreviation Number of Bits Address Data Bus Number of Width Access States Module DTC transfer count register A CRA 16 16/32 1 DTC DTC transfer count register B CRB 16 16/32 1 H'EBC0 to H'EFBF D/A data register_0 DADR_0 8 H'FDAC 8 2 D/A data register _1 DADR_1 8 H'FDAD 8 2 D/A D/A control register DACR 8 H'FDAE 8 2 Serial control register X SCRX 8 H'FDB4 8 2 FLASH Standby control register SBYCR 8 H'FDE4
H8S/2215 Group Section 23 List of Registers Register Name Abbreviation Number of Bits Address Data Bus Number of Width Access States Module Port A data direction register PADDR 8 H'FE39 8 2 PORT Port B data direction register PBDDR 8 H'FE3A 8 2 Port C data direction register PCDDR 8 H'FE3B 8 2 Port D data direction register PDDDR 8 H'FE3C 8 2 Port E data direction register PEDDR 8 H'FE3D 8 2 Port F data direction register PFDDR 8 H'FE3E 8 2 Port G data direction r
H8S/2215 Group Section 23 List of Registers Register Name Abbreviation Number of Bits Address Data Bus Number of Width Access States Module Memory address register 0A H MAR0AH 16 H'FEE0 16 2 DMAC Memory address register 0A L MAR0AL 16 H'FEE2 16 2 I/O address register 0A IOAR0A 16 H'FEE4 16 2 Transfer count register 0A ETCR0A 16 H'FEE6 16 2 Memory address register 0B H MAR0BH 16 H'FEE8 16 2 Memory address register 0B L MAR0BL 16 H'FEEA 16 2 I/O address register 0B
H8S/2215 Group Section 23 List of Registers Register Name Abbreviation Number of Bits Address Data Bus Number of Width Access States Module Timer general register B_0 TGRB_0 16 H'FF1A 16 TPU_0 Timer general register C_0 TGRC_0 16 H'FF1C 16 2 Timer general register D_0 TGRD_0 16 H'FF1E 16 2 2 Timer control register_1 TCR_1 8 H'FF20 16 2 Timer mode register_1 TMDR_1 8 H'FF21 16 2 Timer I/O control register _1 TIOR_1 8 H'FF22 16 2 Timer interrupt enable register _1
H8S/2215 Group Section 23 List of Registers Register Name Abbreviation Number of Bits Address Data Bus Number of Width Access States Module Time constant register B1 TCORB_1 8 H'FF6F 8 2 TMR_1 Timer counter_0 TCNT_0 8 H'FF70 8 2 TMR_0 Timer counter_1 TCNT_1 8 H'FF71 8 2 TMR_1 Timer control/status register TCSR 8 H'FF74 16 2 WDT Timer counter TCNT 8 H'FF74 16 2 16 2 16 2 16 2 (write) Timer counter TCNT 8 H'FF75 (read) Reset control/status register RSTCSR 8
H8S/2215 Group Section 23 List of Registers Register Name Abbreviation Number of Bits Address Data Bus Number of Width Access States Module A/D data register AL ADDRAL 8 H'FF91 8 2 A/D A/D data register BH ADDRBH 8 H'FF92 8 2 A/D data register BL ADDRBL 8 H'FF93 8 2 A/D data register CH ADDRCH 8 H'FF94 8 2 A/D data register CL ADDRCL 8 H'FF95 8 2 A/D data register DH ADDRDH 8 H'FF96 8 2 A/D data register DL ADDRDL 8 H'FF97 8 2 A/D control/status register AD
Section 23 List of Registers 23.2 H8S/2215 Group Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, so 16-bit registers are shown as two lines and 32-bit registers as four lines. Page 708 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 23 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module UEPIRnn_0*1 D39 D38 D37 D36 D35 D34 D33 D32 USB 1 UEPIRnn_1* D31 D30 D29 D28 D27 D26 D25 D24 1 UEPIRnn_2* D23 D22 D21 D20 D19 D18 D17 D16 1 UEPIRnn_3* D15 D14 D13 D12 D11 D10 D9 D8 1 UEPIRnn_4* D7 D6 D5 D4 D3 D2 D1 D0 UCTLR FADSEL SFME UCKS3 UCKS2 UCKS1 UCKS0 UIFRST UDCRST UTSTRA ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ UDMAR EP4oT1 EP4oT0 EP4
H8S/2215 Group Section 23 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 UIER0 BRSTE ⎯ EP1iTRE UIER1 ⎯ ⎯ EP3iTFE UIER2 ⎯ ⎯ EP5iTRE EP5iTSE ⎯ Bit 1 Bit 0 Module EP1iTSE EP0oTSE EP0iTRE EP3iTRE ⎯ EP2o EP0iTSE SetupTSE USB EP2iTRE EP2i EP4iTRE EP4i READYE EP4o EMPTYE READYE UIER3 CK48 SOFE SETCE SETIE ⎯ SPRSiE EMPTYE ⎯ VBUSiE READYE UISR0 BRSTS ⎯ EP1iTRS EP1iTSS EP0oTSS EP0iTRS EP0iTSS SetupTSS UISR1 ⎯ ⎯ EP3iTFS EP3iTRS ⎯ EP2
H8S/2215 Group Section 23 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module DADR_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D/A DADR_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DACR DAOE1 DAOE0 DAE ⎯ ⎯ ⎯ ⎯ ⎯ SCRX ⎯ ⎯ ⎯ ⎯ FLSHE ⎯ ⎯ ⎯ FLASH SBYCR SSBY STS2 STS1 STS0 OPE ⎯ ⎯ ⎯ SYSTEM SYSCR ⎯ ⎯ INTM1 INTM0 NMIEG MRESE ⎯ RAME SCKCR PSTOP ⎯ ⎯ ⎯ ⎯ SCK2 SCK1 SCK0 MDCR ⎯ ⎯ ⎯ ⎯ ⎯ MDS2
H8S/2215 Group Section 23 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PORT PBPCR PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR PCPCR PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR PDPCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR PEPCR PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR P3ODR ⎯ P36ODR P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR PAODR ⎯ ⎯ ⎯ ⎯ PA3ODR PA2OD
H8S/2215 Group Section 23 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MAR0BH ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DMAC Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOAR0B Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ETCR0B Bit 15 Bit 14 Bit 13 Bit 12 B
H8S/2215 Group Section 23 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TPU_0 TCR_0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_0 ⎯ ⎯ BFB BFA MD3 MD2 MD1 MD0 TIORH_0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIORL_0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TIER_0 TTGE ⎯ ⎯ TCIEV TGIED TGIEC TGIEB TGIEA TSR_0 ⎯ ⎯ ⎯ TCFV TGFD TGFC TGFB TGFA TCNT_0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit
H8S/2215 Group Section 23 List of Registers Register Name Bit 7 Bit 6 TCR_2 ⎯ CCLR1 CCLR0 CKEG1 TMDR_2 ⎯ ⎯ ⎯ ⎯ TIOR_2 IOB3 IOB2 IOB1 IOB0 TIER_2 TTGE ⎯ TCIEU TCIEV TSR_2 TCFD ⎯ TCFU TCNT_2 Bit 15 Bit 14 Bit 7 Bit 6 Bit 15 Bit 7 TGRB_2 Bit 15 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DMAWER ⎯ ⎯ ⎯ ⎯ WE1B WE1A WE0B WE0A DMACR0A*2 DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 DMACR0A*3 DTSZ SAID SAIDE BLKDIR BLKE ⎯ ⎯ ⎯ DMACR0B*2 DTSZ DTID
H8S/2215 Group Section 23 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCR_0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_0 TCR_1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_1 TMR_0 TCSR_0 CMFB CMFA OVF ADTE 0S3 OS2 OS1 OS0 TCSR_1 CMFB CMFA OVF ⎯ 0S3 OS2 OS1 OS0 TMR_1 TCORA_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR_0 TCORA_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR_1
H8S/2215 Group Section 23 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D ADDRAL AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ AD2 ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 ADDRBL AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ADDRCH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDRCL AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ADDRDH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDRDL AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ADCSR ADF ADIE ADST SCAN CH3 CH2 CH1 CH
H8S/2215 Group Section 23 List of Registers 23.
H8S/2215 Group Section 23 List of Registers Register Name Power-on Reset Manual Reset HighSpeed MediumSpeed Sleep Module Stop Software Standby Hardware Standby Module UIER1 Initialized* ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized USB UIER2 Initialized* ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized UIER3 Initialized* ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized UISR0 Initialized* ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized UISR1 Initialized* ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized UISR2 Initialized* ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized UISR3 Initializ
H8S/2215 Group Section 23 List of Registers Register Name Power-on Reset Manual Reset HighSpeed MediumSpeed Sleep Module Stop Software Standby Hardware Standby PFCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized BSC LPWRCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SYSTEM SEMR_0 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SCI_0 ISCRH Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ Initialized INT ISCRL Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ Initialized IER Initialized Initialized
H8S/2215 Group Section 23 List of Registers Register Name Power-on Reset Manual Reset HighSpeed MediumSpeed Sleep Module Stop Software Standby Hardware Standby Module TSTR Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TPU TSYR Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ Initialized IPRA Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ Initialized IPRB Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ Initialized IPRC Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ Initialized IPRD Initialized Initializ
H8S/2215 Group Section 23 List of Registers Register Name Power-on Reset Manual Reset HighSpeed MediumSpeed Sleep Module Stop Software Standby Hardware Standby Module P1DR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PORT P3DR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized P7DR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PADR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PBDR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PCDR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PDDR Initialized ⎯ ⎯ ⎯
H8S/2215 Group Register Name Section 23 List of Registers Power-on Reset Manual Reset HighSpeed MediumSpeed Sleep Module Stop Software Standby Hardware Standby Module DMAC DMAWER Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DMACR0A Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DMACR0B Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DMACR1A Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DMACR1B Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DMABCR Initia
H8S/2215 Group Section 23 List of Registers Register Name Power-on Reset Manual Reset HighSpeed MediumSpeed Sleep Module Stop Software Standby Hardware Standby Module SMR_2 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SCI_2 BRR_2 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SCR_2 Initialized Initialized ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TDR_2 Initialized Initialized ⎯ ⎯ ⎯ Initialized Initialized Initialized SSR_2 Initialized Initialized ⎯ ⎯ ⎯ Initialized Initial
H8S/2215 Group Section 24 Electrical Characteristics (H8S/2215) Section 24 Electrical Characteristics (H8S/2215) 24.1 Absolute Maximum Ratings Table 24.1 lists the absolute maximum ratings. Table 24.1 Absolute Maximum Ratings Item Symbol Value Power supply voltage VCC, PLLVCC, –0.3 to +4.3 DrVCC Unit V Input voltage (except ports 4 and 9) Vin –0.3 to VCC +0.3 V Input voltage (ports 4 and 9) Vin –0.3 to AVCC +0.3 V Reference voltage Vref –0.3 to AVCC +0.
H8S/2215 Group Section 24 Electrical Characteristics (H8S/2215) 24.2 Power Supply Voltage and Operating Frequency Range Power supply voltage and operating frequency ranges (shaded areas) are shown in figure 24.1. (1) When on-chip USB is not used f (MHz) system clock 16.0 13.0 0 2.7 3.0 3.6 Vcc, PLLVcc, DrVcc, AVcc (V) 3.6 Vcc, PLLVcc, DrVcc, AVcc (V) (2) When on-chip USB is used f (MHz) system clock 16.0 13.0 0 2.7 3.
H8S/2215 Group 24.3 Section 24 Electrical Characteristics (H8S/2215) DC Characteristics Table 24.2 lists the DC characteristics. Table 24.3 lists the permissible output currents. Table 24.2 DC Characteristics Conditions: VCC = PLLVCC = DrVCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.
H8S/2215 Group Section 24 Electrical Characteristics (H8S/2215) Item Output low voltage Symbol All output pins VOL Input leakage RES, STBY, | Iin | current NMI, MD2 to 5 MD0, FWE* , VBUS,UBPM Ports 4, 9 3-state leak current (off status) | Iin | Ports 1, 3, 7, A | ITSI | to G Test Conditions Min. Typ. Max. Unit — — 0.4 V IOH = 0.4 mA — — 0.4 V IOL = 0.8 mA — — 1.0 µA Vin = 0.5 V to VCC – 0.5 V — — 1.0 µA Vin = 0.5 V to AVCC – 0.5 V — — 1.0 µA Vin = 0.5 V to VCC – 0.
H8S/2215 Group Section 24 Electrical Characteristics (H8S/2215) Item Symbol Min. Typ. Max. Unit Test Conditions Reference During A/D power supply conversion current Idle AlCC — 1.3 2.5 mA Vref = 3.3 V — 0.01 5.0 µA RAM standby voltage VRAM 2.0 — — V Notes: 1. If the A/D or D/A converter is not used, the AVCC, Vref, and AVSS pins should not be open. Even if the A/D or D/A converter is not used, connect the AVCC and Vref pins to VCC and the AVSS pin to VSS, respectively.
H8S/2215 Group Section 24 Electrical Characteristics (H8S/2215) Table 24.3 Permissible Output Currents Conditions: VCC = PLLVCC = DrVCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)* Item Symbol Min. Typ. Max. Unit Permissible output low current (per pin) All output pins VCC = 2.7 to 3.6 V IOL — — 1.
H8S/2215 Group 24.4.1 Section 24 Electrical Characteristics (H8S/2215) Clock Timing Table 24.4 lists the clock timing Table 24.4 Clock Timing Conditions: VCC = PLLVCC = DrVCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 13 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions Clock cycle time tcyc 62.5 76.9 ns Figure 24.
H8S/2215 Group Section 24 Electrical Characteristics (H8S/2215) tcyc tCH tCf φ tCL tCr Figure 24.3 System Clock Timing EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES φ Figure 24.4 Oscillation Stabilization Timing Page 732 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group 24.4.2 Section 24 Electrical Characteristics (H8S/2215) Control Signal Timing Table 24.5 lists the control signal timing. Table 24.5 Control Signal Timing Conditions: VCC = PLLVCC = DrVCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 13 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min. Max.
H8S/2215 Group Section 24 Electrical Characteristics (H8S/2215) φ tNMIS tNMIH NMI tNMIW IRQ tIRQW tIRQS tIRQH IRQ edge input tIRQS IRQ level input Figure 24.6 Interrupt Input Timing Page 734 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group 24.4.3 Section 24 Electrical Characteristics (H8S/2215) Bus Timing Table 24.6 shows, Bus Timing. Table 24.6 Bus Timing Conditions: VCC = PLLVCC = DrVCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 13 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Address delay time Address setup time Address hold time tAH 0.
H8S/2215 Group Section 24 Electrical Characteristics (H8S/2215) T1 T2 φ tAD A23 to A0 tCSD tAH tAS CS7 to CS0 tASD tASD AS tRSD1 RD (read) tRSD2 tACC2 tAS tACC3 tRDS tRDH D15 to D0 (read) tWRD2 HWR, LWR (write) tWRD2 tAH tAS tWDD tWSW1 tWDH D15 to D0 (write) Figure 24.7 Basic Bus Timing (Two-State Access) Page 736 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 24 Electrical Characteristics (H8S/2215) T1 T2 T3 φ tAD A23 to A0 tCSD tAS tAH CS7 to CS0 tASD tASD AS tRSD1 RD (read) tACC4 tRSD2 tAS tRDS tRDH tACC5 D15 to D0 (read) tWRD1 tWRD2 HWR, LWR (write) tAH tWDD tWDS tWSW2 tWDH D15 to D0 (write) Figure 24.8 Basic Bus Timing (Three-State Access) REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 24 Electrical Characteristics (H8S/2215) T1 T2 TW T3 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH tWTS tWTH WAIT Figure 24.9 Basic Bus Timing (Three-State Access with One Wait State) Page 738 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 24 Electrical Characteristics (H8S/2215) T1 T2 or T3 T1 T2 φ tAD A23 to A0 tAH tAS CS0 tASD tASD AS tRSD2 RD (read) tACC3 tRDS tRDH D15 to D0 (read) Figure 24.10 Burst ROM Access Timing (Two-State Access) REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 24 Electrical Characteristics (H8S/2215) φ tBRQS tBRQS BREQ tBACD tBACD BACK tBZD tBZD A23 to A0, CS7 to CS0, AS, RD, HWR, LWR Figure 24.11 External Bus Release Timing Page 740 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group 24.4.4 Section 24 Electrical Characteristics (H8S/2215) Timing of On-Chip Supporting Modules Table 24.7 lists the timing of on-chip supporting modules. Table 24.7 Timing of On-Chip Supporting Modules Conditions: VCC = PLLVCC = DrVCC =2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 13 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item I/O port TPU TMR Symbol Min. Max.
H8S/2215 Group Section 24 Electrical Characteristics (H8S/2215) Item SCI Symbol Input clock cycle Min. Max. Unit Test Conditions Asynchro- tScyc nous 4 — tcyc Figure 24.18 Synchronous 6 — Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr — 1.5 tcyc Input clock fall time tSCKf — 1.
H8S/2215 Group Section 24 Electrical Characteristics (H8S/2215) T1 T2 φ tPRS tPRH Ports 1, 3, 4, 7, 9, A to G (read) tPWD Ports 1, 3, 7, A to G (write) Figure 24.12 I/O Port Input/Output Timing φ tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TIOCC0, TIOCD0 Figure 24.13 TPU Input/Output Timing φ tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 24.14 TPU Clock Input Timing REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 24 Electrical Characteristics (H8S/2215) φ tTMOD TMO0, TMO1 Figure 24.15 8-bit Timer Output Timing φ tTMCS tTMCS TMCI01 tTMCWL tTMCWH Figure 24.16 8-bit Timer Clock Input Timing φ tTMRS TMRI01 Figure 24.17 8-bit Timer Reset Input Timing tSCKW tSCKr tSCKf SCK0 to SCK2 tScyc Figure 24.18 SCK Clock Input Timing Page 744 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 24 Electrical Characteristics (H8S/2215) SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS tRXH RxD0 to RxD2 (receive data) Figure 24.19 SCI Input/Output Timing (Clock Synchronous Mode) φ tTRGS ADTRG Figure 24.20 A/D Converter External Trigger Input Timing ttcyc tTCKH tTCKL TCK Figure 24.21 Boundary Scan TCK Input Timing TCK tTRSS tTRSS TRST tTRSW Figure 24.22 Boundary Scan TRST Input Timing (At Reset Hold) REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 24 Electrical Characteristics (H8S/2215) TCK tTDIS tTDIH tTMSS tTMSH TDI TMS tTDOD tTDOD TDO Figure 24.23 Boundary Scan Data Transmission Timing Page 746 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group 24.5 Section 24 Electrical Characteristics (H8S/2215) USB Characteristics Table 24.8 lists the USB characteristics (USD+ and USD- pins) when the on-chip USB transceiver is used. Table 24.8 USB Characteristics (USD+ and USD- pins) when On-Chip USB Transceiver Is Used Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 13 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (widerange specifications) Item Symbol Min. Max.
H8S/2215 Group Section 24 Electrical Characteristics (H8S/2215) Rise Time USD+, USD- Fall Time 90% VCRS 90% 10% Differential Date Lines 10% tR tF Figure 24.24 Data Signal Timing USD+ Rs = 24 Ω Test Point CL = 50 pF USD- Rs = 24 Ω Test Point CL = 50 pF Figure 24.25 Test Load Circuit Page 748 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group 24.6 Section 24 Electrical Characteristics (H8S/2215) A/D Conversion Characteristics Table 24.9 lists the A/D conversion characteristics. Table 24.9 A/D Conversion Characteristics Conditions: VCC = PLLVCC = DrVCC = 2.7 V to 3.6 V*, AVCC = 2.7 V to 3.6 V*, Vref = 2.7 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 13 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Min. Typ. Max.
H8S/2215 Group Section 24 Electrical Characteristics (H8S/2215) 24.8 Flash Memory Characteristics Table 24.11 Flash Memory Characteristics Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, Ta = –20 to +75°C (Programming/erasing operating temperature range) Item Symbol Min.
H8S/2215 Group Section 24 Electrical Characteristics (H8S/2215) 4. Maximum programming time value tp (max.) = Wait time after P1 bit set (z) × maximum programming count (N1 + N2) = (Z0 + Z2) × 6 + Z1 × 994 5. Maximum erasure time value tE (max.) = Wait time after E1 bit set (z) × maximum erasure count (N) 6. Minimum number of times for which all characteristics are guaranteed after rewriting (Guarantee range is 1 to minimum value). 7.
Section 24 Electrical Characteristics (H8S/2215) Page 752 of 846 H8S/2215 Group REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) Section 25 Electrical Characteristics (H8S/2215R) 25.1 Absolute Maximum Ratings Table 25.1 lists the absolute maximum ratings. Table 25.1 Absolute Maximum Ratings Item Symbol Value Power supply voltage VCC, PLLVCC, –0.3 to +4.3 DrVCC Unit V Input voltage (except ports 4 and 9) Vin –0.3 to VCC +0.3 V Input voltage (ports 4 and 9) Vin –0.3 to AVCC +0.3 V Reference voltage Vref –0.3 to AVCC +0.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) 25.2 Power Supply Voltage and Operating Frequency Range Power supply voltage and operating frequency ranges (shaded areas) are shown in figure 25.1. (1) When on-chip USB is not used f (MHz) system clock 24.0 16.0 13.0 0 2.7 3.0 3.6 Vcc, PLLVcc, DrVcc, AVcc (V) 3.6 Vcc, PLLVcc, DrVcc, AVcc (V) (2) When on-chip USB is used f (MHz) system clock 24.0 16.0 13.0 0 2.7 3.
H8S/2215 Group 25.3 Section 25 Electrical Characteristics (H8S/2215R) DC Characteristics Table 25.2 lists the DC characteristics. Table 25.3 lists the permissible output currents. Table 25.2 DC Characteristics Conditions: VCC = PLLVCC = DrVCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), 1 Ta = –40°C to +85°C (wide-range specifications)* Symbol Min. Item Typ. IRQ0 to IRQ5 VT VCC × 0.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) Symbol Min. Item Output low voltage All output pins VOL Input leakage current RES, STBY, NMI, MD2 to 5 MD0, FWE* , VBUS,UBPM Ports 4, 9 Typ. Max. Test Unit Conditions — — 0.4 V IOH = 0.4 mA — — 0.4 V IOL = 0.8 mA | Iin | — — 1.0 µA Vin = 0.5 V to VCC – 0.5 V | Iin | — — 1.0 µA Vin = 0.5 V to AVCC – 0.5 V 3-state leak Ports 1, 3, 7, A | ITSI | current (off to G status) — — 1.0 µA Vin = 0.5 V to VCC – 0.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) Item Current All modules 2 dissipation* stopped Symbol Min. 3 — ICC* Analog power supply current During A/D conversion Reference power supply current During A/D conversion AlCC Idle AlCC Idle RAM standby voltage VRAM Max. Test Unit Conditions 15 — (VCC = 3.3 V) mA f = 16 MHz (reference value) 21 — (VCC = 3.3 V) mA f = 24 MHz (reference value) — 1.0 10 µA Ta ≤ 50°C — — 50 µA 50°C < Ta — 0.3 1.5 mA AVCC = 3.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) Table 25.3 Permissible Output Currents Conditions: VCC = PLLVCC = DrVCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)* Item Symbol Min. Typ. Max. Unit Permissible output low current (per pin) All output pins VCC = 2.7 to 3.6 V IOL — — 1.
H8S/2215 Group 25.4.1 Section 25 Electrical Characteristics (H8S/2215R) Clock Timing Table 25.4 lists the clock timing Table 25.4 Clock Timing Condition A: VCC = PLLVCC = DrVCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 13 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) Condition A Condition B Item Symbol Min. Max. Min. Max. Unit Test Conditions External clock output stabilization delay time tDEXT 500 — 500 — µs Figure 25.4 USB operating clock (48 MHz) stabilization time tOSC3 8 — 8 — ms VCC = 3.0 V to 3.6 V USB operating clock (48 f48 MHz) oscillator frequency 48 4.8 MHz USB operating clock (48 MHz) cycle time 20.8 20.8 ns f48 tcyc tCH tCf φ tCL tCr Figure 25.
H8S/2215 Group 25.4.2 Section 25 Electrical Characteristics (H8S/2215R) Control Signal Timing Table 25.5 lists the control signal timing. Table 25.5 Control Signal Timing Condition A: VCC = PLLVCC = DrVCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 13 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) φ tRESS tRESS tMRESS tMRESS RES tRESW MRES tMRESW Figure 25.5 Reset Input Timing φ tNMIS tNMIH NMI tNMIW IRQ tIRQW tIRQS tIRQH IRQ edge input tIRQS IRQ level input Figure 25.6 Interrupt Input Timing Page 762 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group 25.4.3 Section 25 Electrical Characteristics (H8S/2215R) Bus Timing Table 25.6 shows, Bus Timing. Table 25.6 Bus Timing Condition A: VCC = PLLVCC = DrVCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 13 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) Condition A Item Symbol Min. Max. WR pulse width 1 tWSW1 1.0 × tcyc — – 30 WR pulse width 2 tWSW2 Write data delay time Condition B Unit Test Conditions 1.0 × tcyc — – 20 ns Figure 25.7 1.5 × tcyc — – 30 1.5 × tcyc — – 20 ns Figure 25.8 tWDD — — 30 ns Figures 25.7, 25.8 Write data setup time tWDS 0.5 × tcyc — – 30 0.5 × tcyc — – 20 ns Figure 25.8 Write data hold time tWDH 0.5 × tcyc — – 15 0.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) T1 T2 φ tAD A23 to A0 tCSD tAH tAS CS7 to CS0 tASD tASD AS tRSD1 RD (read) tRSD2 tACC2 tAS tACC3 tRDS tRDH D15 to D0 (read) tWRD2 HWR, LWR (write) tWRD2 tAH tAS tWDD tWSW1 tWDH D15 to D0 (write) Figure 25.7 Basic Bus Timing (Two-State Access) REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) T1 T2 T3 φ tAD A23 to A0 tCSD tAS tAH CS7 to CS0 tASD tASD AS tRSD1 RD (read) tACC4 tRSD2 tAS tRDS tRDH tACC5 D15 to D0 (read) tWRD1 tWRD2 HWR, LWR (write) tAH tWDD tWDS tWSW2 tWDH D15 to D0 (write) Figure 25.8 Basic Bus Timing (Three-State Access) Page 766 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) T1 T2 TW T3 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH tWTS tWTH WAIT Figure 25.9 Basic Bus Timing (Three-State Access with One Wait State) REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) T1 T2 or T3 T1 T2 φ tAD A23 to A0 tAH tAS CS0 tASD tASD AS tRSD2 RD (read) tACC3 tRDS tRDH D15 to D0 (read) Figure 25.10 Burst ROM Access Timing (Two-State Access) Page 768 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) φ tBRQS tBRQS BREQ tBACD tBACD BACK tBZD tBZD A23 to A0, CS7 to CS0, AS, RD, HWR, LWR Figure 25.11 External Bus Release Timing REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) 25.4.4 Timing of On-Chip Supporting Modules Table 25.7 lists the timing of on-chip supporting modules. Table 25.7 Timing of On-Chip Supporting Modules Condition A: VCC = PLLVCC = DrVCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 13 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLLVCC = DrVCC = 3.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) Condition A Item TMR SCI Symbol Min. Max. Min. Max. Unit Test Conditions tcyc Figure 25.16 tcyc Figure 25.18 Timer clock pulse width Single edge tTMCWH 1.5 — 1.5 — Both edges tTMCWL 2.5 — 2.5 — Input clock cycle Asynch- tScyc ronous 4 — 4 — Synchronous 6 — 6 — 0.4 0.6 0.4 0.6 tScyc tcyc Input clock pulse tSCKW width Input clock rise time tSCKr — 1.5 — 1.5 Input clock fall time tSCKf — 1.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) T1 T2 φ tPRS tPRH Ports 1, 3, 4, 7, 9, A to G (read) tPWD Ports 1, 3, 7, A to G (write) Figure 25.12 I/O Port Input/Output Timing φ tTOCD Output compare output* tTICS Input capture input* Note : * TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TIOCC0, TIOCD0 Figure 25.13 TPU Input/Output Timing φ tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 25.14 TPU Clock Input Timing Page 772 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) φ tTMOD TMO0, TMO1 Figure 25.15 8-bit Timer Output Timing φ tTMCS tTMCS TMCI01 tTMCWL tTMCWH Figure 25.16 8-bit Timer Clock Input Timing φ tTMRS TMRI01 Figure 25.17 8-bit Timer Reset Input Timing tSCKW tSCKr tSCKf SCK0 to SCK2 tScyc Figure 25.18 SCK Clock Input Timing REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS tRXH RxD0 to RxD2 (receive data) Figure 25.19 SCI Input/Output Timing (Clock Synchronous Mode) φ tTRGS ADTRG Figure 25.20 A/D Converter External Trigger Input Timing ttcyc tTCKH tTCKL TCK Figure 25.21 Boundary Scan TCK Input Timing TCK tTRSS tTRSS TRST tTRSW Figure 25.22 Boundary Scan TRST Input Timing (At Reset Hold) Page 774 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) TCK tTDIS tTDIH tTMSS tTMSH TDI TMS tTDOD tTDOD TDO Figure 25.23 Boundary Scan Data Transmission Timing REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) 25.5 USB Characteristics Table 25.8 lists the USB characteristics (USD+ and USD- pins) when the on-chip USB transceiver is used. Table 25.8 USB Characteristics (USD+ and USD- pins) when On-Chip USB Transceiver Is Used Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 13 MHz to 24 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (widerange specifications) Item Symbol Min. Max.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) Rise Time USD+, USD- Fall Time 90% VCRS 90% 10% Differential Date Lines 10% tR tF Figure 25.24 Data Signal Timing USD+ Rs = 24 Ω Test Point CL = 50 pF USD- Rs = 24 Ω Test Point CL = 50 pF Figure 25.25 Test Load Circuit REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) 25.6 A/D Conversion Characteristics Table 25.9 lists the A/D conversion characteristics. Table 25.9 A/D Conversion Characteristics Condition A: VCC = PLLVCC = DrVCC = 2.7 V to 3.6 V*, AVCC = 2.7 V to 3.6 V*, Vref = 2.7 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 13 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V*, AVCC = 3.
H8S/2215 Group 25.7 Section 25 Electrical Characteristics (H8S/2215R) D/A Conversion Characteristics Table 25.10 lists the D/A conversion characteristics. Table 25.10 D/A Conversion Characteristics Condition A: VCC = PLLVCC = DrVCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 13 MHz to 16 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Condition B: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.
H8S/2215 Group Section 25 Electrical Characteristics (H8S/2215R) Item Programming Common Erase Wait time after PSU1 bit setting*1 Wait time after P1 bit setting*1*4 Symbol Min. y 50 z0 28 z1 198 Typ. Max.
H8S/2215 Group 25.9 Section 25 Electrical Characteristics (H8S/2215R) Usage Note General Notice during Design for Printed Circuit Board: Measures for radiation noise caused by the transient current in this LSI should be taken into consideration. The examples of the measures are shown below. • To use a multilayer printed circuit board which includes layers for Vcc and GND. • To mount by-pass capacitors (approximately 0.
Section 25 Electrical Characteristics (H8S/2215R) Page 782 of 846 H8S/2215 Group REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) Section 26 Electrical Characteristics (H8S/2215T) 26.1 Absolute Maximum Ratings Table 26.1 lists the absolute maximum ratings. Table 26.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC, PLLVCC, –0.3 to +4.3 DrVCC V Input voltage (except ports 4 and 9) Vin –0.3 to VCC +0.3 V Input voltage (ports 4 and 9) Vin –0.3 to AVCC +0.3 V Reference voltage Vref –0.3 to AVCC +0.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) 26.3 DC Characteristics Table 26.2 lists the DC characteristics. Table 26.3 lists the permissible output currents. Table 26.2 DC Characteristics Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), 1 Ta = –40°C to +85°C (wide-range specifications)* Symbol Min. Item Typ. IRQ0 to IRQ5 VT VCC × 0.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) Symbol Min. Item Output low voltage All output pins VOL Input leakage current RES, STBY, NMI, MD2 to 5 MD0, FWE* , VBUS,UBPM Ports 4, 9 Typ. Max. Test Unit Conditions — — 0.4 V IOH = 0.4 mA — — 0.4 V IOL = 0.8 mA | Iin | — — 1.0 µA Vin = 0.5 V to VCC – 0.5 V | Iin | — — 1.0 µA Vin = 0.5 V to AVCC – 0.5 V 3-state leak Ports 1, 3, 7, A | ITSI | current (off to G status) — — 1.0 µA Vin = 0.5 V to VCC – 0.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) Item Current All modules 2 dissipation* stopped Symbol Min. 3 — ICC* Analog power supply current During A/D conversion Reference power supply current During A/D conversion AlCC Idle AlCC Idle RAM standby voltage VRAM Max. Test Unit Conditions 15 — (VCC = 3.3 V) mA f = 16 MHz (reference value) 21 — (VCC = 3.3 V) mA f = 24 MHz (reference value) — 1.0 10 µA Ta ≤ 50°C — — 50 µA 50°C < Ta — 0.3 1.5 mA AVCC = 3.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) Table 26.3 Permissible Output Currents Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)* Item Symbol Min. Typ. Max. Unit Permissible output low current (per pin) All output pins VCC = 3.0 to 3.6 V IOL — — 1.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) 26.4.1 Clock Timing Table 26.4 lists the clock timing Table 26.4 Clock Timing Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 16 MHz, 24 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions Clock cycle time tcyc 41.6 62.5 ns Figure 26.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) tcyc tCH tCf φ tCL tCr Figure 26.3 System Clock Timing EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES φ Figure 26.4 Oscillation Stabilization Timing REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) 26.4.2 Control Signal Timing Table 26.5 lists the control signal timing. Table 26.5 Control Signal Timing Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 16 MHz, 24 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min. Max.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) φ tNMIS tNMIH NMI tNMIW IRQ tIRQW tIRQS tIRQH IRQ edge input tIRQS IRQ level input Figure 26.6 Interrupt Input Timing REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) 26.4.3 Bus Timing Table 26.6 shows, Bus Timing. Table 26.6 Bus Timing Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 16 MHz, 24 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions Address delay time tAD — 30 ns Address setup time tAS 0.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) Item Symbol Min. Max. Unit WAIT hold time tWTH 5 — ns BREQ setup time tBRQS 25 — ns BACK delay time tBACD — 40 ns Bus-floating time tBZD — 50 ns T1 Test Conditions Figure 26.11 T2 φ tAD A23 to A0 tCSD tAH tAS CS7 to CS0 tASD tASD AS tRSD1 RD (read) tRSD2 tACC2 tAS tACC3 tRDS tRDH D15 to D0 (read) tWRD2 HWR, LWR (write) tWRD2 tAH tAS tWDD tWSW1 tWDH D15 to D0 (write) Figure 26.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) T1 T2 T3 φ tAD A23 to A0 tCSD tAS tAH CS7 to CS0 tASD tASD AS tRSD1 RD (read) tACC4 tRSD2 tAS tRDS tRDH tACC5 D15 to D0 (read) tWRD1 tWRD2 HWR, LWR (write) tAH tWDD tWDS tWSW2 tWDH D15 to D0 (write) Figure 26.8 Basic Bus Timing (Three-State Access) Page 794 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) T1 T2 TW T3 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH tWTS tWTH WAIT Figure 26.9 Basic Bus Timing (Three-State Access with One Wait State) REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) T1 T2 or T3 T1 T2 φ tAD A23 to A0 tAH tAS CS0 tASD tASD AS tRSD2 RD (read) tACC3 tRDS tRDH D15 to D0 (read) Figure 26.10 Burst ROM Access Timing (Two-State Access) Page 796 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) φ tBRQS tBRQS BREQ tBACD tBACD BACK tBZD tBZD A23 to A0, CS7 to CS0, AS, RD, HWR, LWR Figure 26.11 External Bus Release Timing REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) 26.4.4 Timing of On-Chip Supporting Modules Table 26.7 lists the timing of on-chip supporting modules. Table 26.7 Timing of On-Chip Supporting Modules Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 16 MHz, 24 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item I/O port TPU TMR TMR SCI Symbol Min.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) Item Symbol Min. Max. Unit Test Conditions Boundary TCK cycle time scan TCK high level pulse width tcyc 41.6 — ns Figure 26.21 tTCKH 0.4 0.6 tcyc TCK low level pulse width tTCKL 0.4 0.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) φ tTOCD Output compare output* tTICS Input capture input* Note : * TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TIOCC0, TIOCD0 Figure 26.13 TPU Input/Output Timing φ tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 26.14 TPU Clock Input Timing φ tTMCS tTMCS TMCI01 tTMCWL tTMCWH Figure 26.15 8-bit Timer Output Timing φ tTMCS tTMCS TMCI01 tTMCWL tTMCWH Figure 26.16 8-bit Timer Clock Input Timing Page 800 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) φ tTMRS TMRI01 Figure 26.17 8-bit Timer Reset Input Timing tSCKW tSCKr tSCKf SCK0 to SCK2 tScyc Figure 26.18 SCK Clock Input Timing SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS tRXH RxD0 to RxD2 (receive data) Figure 26.19 SCI Input/Output Timing (Clock Synchronous Mode) φ tTRGS ADTRG Figure 26.20 A/D Converter External Trigger Input Timing REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) ttcyc tTCKH tTCKL TCK Figure 26.21 Boundary Scan TCK Input Timing TCK tTRSS tTRSS TRST tTRSW Figure 26.22 Boundary Scan TRST Input Timing (At Reset Hold) TCK tTDIS tTDIH tTMSS tTMSH TDI TMS tTDOD tTDOD TDO Figure 26.23 Boundary Scan Data Transmission Timing Page 802 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group 26.5 Section 26 Electrical Characteristics (H8S/2215T) USB Characteristics Table 26.8 lists the USB characteristics (USD+ and USD- pins) when the on-chip USB transceiver is used. Table 26.8 USB Characteristics (USD+ and USD- pins) when On-Chip USB Transceiver Is Used Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 16 MHz, 24 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (widerange specifications) Item Symbol Min. Max.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) Rise Time USD+, USD- Fall Time 90% VCRS 90% 10% 10% Differential Date Lines tR tF Figure 26.24 Data Signal Timing Rs = 24 Ω USD+ Test Point CL = 50 pF Rs = 24 Ω USD- Test Point CL = 50 pF Figure 26.25 Test Load Circuit 26.6 A/D Conversion Characteristics Table 26.9 lists the A/D conversion characteristics. Table 26.9 A/D Conversion Characteristics Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V*, AVCC = 3.0 V to 3.
H8S/2215 Group 26.7 Section 26 Electrical Characteristics (H8S/2215T) D/A Conversion Characteristics Table 26.10 lists the D/A conversion characteristics. Table 26.10 D/A Conversion Characteristics Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 16 MHz, 24 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Min. Typ. Max.
H8S/2215 Group Section 26 Electrical Characteristics (H8S/2215T) Item Symbol Wait time after SWE1 bit setting*1 Wait time after SWE1 bit clear*1 Common Erase Min. Typ. Max.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) Section 27 Electrical Characteristics (H8S/2215C) 27.1 Absolute Maximum Ratings Table 27.1 lists the absolute maximum ratings. Table 27.1 Absolute Maximum Ratings Item Symbol Value Power supply voltage VCC, PLLVCC, –0.3 to +4.3 DrVCC Unit V Input voltage (except ports 4 and 9) Vin –0.3 to VCC +0.3 V Input voltage (ports 4 and 9) Vin –0.3 to AVCC +0.3 V Reference voltage Vref –0.3 to AVCC +0.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) 27.2 Power Supply Voltage and Operating Frequency Range Power supply voltage and operating frequency ranges (shaded areas) are shown in figure 27.1. (1) Normal operation f (MHz) system clock 24.0 16.0 0 3.0 3.6 Vcc, PLLVcc, DrVcc, AVcc (V) (2) When USB boot program is executed f (MHz) system clock 24.0 With operation of USB operating clock (48 MHz) provided by PLL 2 or 3 multiplication 16.0 13.0 0 2.7 3.0 3.
H8S/2215 Group 27.3 Section 27 Electrical Characteristics (H8S/2215C) DC Characteristics Table 27.2 lists the DC characteristics. Table 27.3 lists the permissible output currents. Table 27.2 DC Characteristics Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), 1 Ta = –40°C to +85°C (wide-range specifications)* Symbol Min. Item Typ. IRQ0 to IRQ5 VT VCC × 0.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) Symbol Min. Item Output low voltage All output pins VOL Input leakage current RES, STBY, NMI, MD2 to 5 MD0, FWE* , VBUS,UBPM Ports 4, 9 Typ. Max. Test Unit Conditions — — 0.4 V IOH = 0.4 mA — — 0.4 V IOL = 0.8 mA | Iin | — — 1.0 µA Vin = 0.5 V to VCC – 0.5 V | Iin | — — 1.0 µA Vin = 0.5 V to AVCC – 0.5 V 3-state leak Ports 1, 3, 7, A | ITSI | current (off to G status) — — 1.0 µA Vin = 0.5 V to VCC – 0.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) Item Current All modules 2 dissipation* stopped Symbol Min. 3 — ICC* Analog power supply current During A/D conversion Reference power supply current During A/D conversion AlCC Idle AlCC Idle RAM standby voltage VRAM Max. Test Unit Conditions 15 — (VCC = 3.3 V) mA f = 16 MHz (reference value) 21 — (VCC = 3.3 V) mA f = 24 MHz (reference value) — 1.0 10 µA Ta ≤ 50°C — — 50 µA 50°C < Ta — 0.3 1.5 mA AVCC = 3.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) Table 27.3 Permissible Output Currents Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)* Item Symbol Min. Typ. Max. Unit Permissible output low current (per pin) All output pins VCC = 2.7 to 3.6 V IOL — — 1.
H8S/2215 Group 27.4.1 Section 27 Electrical Characteristics (H8S/2215C) Clock Timing Table 27.4 lists the clock timing Table 27.4 Clock Timing Condition: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 16 MHz to 24 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions Clock cycle time tcyc 41.6 62.5 ns Figure 27.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) tcyc tCH tCf φ tCL tCr Figure 27.3 System Clock Timing EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES φ Figure 27.4 Oscillation Stabilization Timing Page 814 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group 27.4.2 Section 27 Electrical Characteristics (H8S/2215C) Control Signal Timing Table 27.5 lists the control signal timing. Table 27.5 Control Signal Timing Condition: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 16 MHz to 24 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min. Max.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) φ tRESS tRESS tMRESS tMRESS RES tRESW MRES tMRESW Figure 27.5 Reset Input Timing φ tNMIS tNMIH NMI tNMIW IRQ tIRQW tIRQS tIRQH IRQ edge input tIRQS IRQ level input Figure 27.6 Interrupt Input Timing Page 816 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group 27.4.3 Section 27 Electrical Characteristics (H8S/2215C) Bus Timing Table 27.6 shows, Bus Timing. Table 27.6 Bus Timing Condition: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 16 MHz to 24 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions Address delay time Address setup time tAD — tAS 0.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) T1 T2 φ tAD A23 to A0 tCSD tAH tAS CS7 to CS0 tASD tASD AS tRSD1 RD (read) tRSD2 tACC2 tAS tACC3 tRDS tRDH D15 to D0 (read) tWRD2 HWR, LWR (write) tWRD2 tAH tAS tWDD tWSW1 tWDH D15 to D0 (write) Figure 27.7 Basic Bus Timing (Two-State Access) Page 818 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) T1 T2 T3 φ tAD A23 to A0 tCSD tAS tAH CS7 to CS0 tASD tASD AS tRSD1 RD (read) tACC4 tRSD2 tAS tRDS tRDH tACC5 D15 to D0 (read) tWRD1 tWRD2 HWR, LWR (write) tAH tWDD tWDS tWSW2 tWDH D15 to D0 (write) Figure 27.8 Basic Bus Timing (Three-State Access) REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) T1 T2 TW T3 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH tWTS tWTH WAIT Figure 27.9 Basic Bus Timing (Three-State Access with One Wait State) Page 820 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) T1 T2 or T3 T1 T2 φ tAD A23 to A0 tAH tAS CS0 tASD tASD AS tRSD2 RD (read) tACC3 tRDS tRDH D15 to D0 (read) Figure 27.10 Burst ROM Access Timing (Two-State Access) REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) φ tBRQS tBRQS BREQ tBACD tBACD BACK tBZD tBZD A23 to A0, CS7 to CS0, AS, RD, HWR, LWR Figure 27.11 External Bus Release Timing Page 822 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group 27.4.4 Section 27 Electrical Characteristics (H8S/2215C) Timing of On-Chip Supporting Modules Table 27.7 lists the timing of on-chip supporting modules. Table 27.7 Timing of On-Chip Supporting Modules Condition: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 16 MHz to 24 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Symbol Min. Max.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) Item Symbol Min. Max. Unit Test Conditions Boundary TCK cycle time scan TCK high level pulse width tcyc 41.6 — ns Figure 27.21 tTCKH 0.4 0.6 tcyc TCK low level pulse width tTCKL 0.4 0.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) T1 T2 φ tPRS tPRH Ports 1, 3, 4, 7, 9, A to G (read) tPWD Ports 1, 3, 7, A to G (write) Figure 27.12 I/O Port Input/Output Timing φ tTOCD Output compare output* tTICS Input capture input* Note : * TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TIOCC0, TIOCD0 Figure 27.13 TPU Input/Output Timing φ tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 27.14 TPU Clock Input Timing REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) φ tTMOD TMO0, TMO1 Figure 27.15 8-bit Timer Output Timing φ tTMCS tTMCS TMCI01 tTMCWL tTMCWH Figure 27.16 8-bit Timer Clock Input Timing φ tTMRS TMRI01 Figure 27.17 8-bit Timer Reset Input Timing tSCKW tSCKr tSCKf SCK0 to SCK2 tScyc Figure 27.18 SCK Clock Input Timing Page 826 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS tRXH RxD0 to RxD2 (receive data) Figure 27.19 SCI Input/Output Timing (Clock Synchronous Mode) φ tTRGS ADTRG Figure 27.20 A/D Converter External Trigger Input Timing ttcyc tTCKH tTCKL TCK Figure 27.21 Boundary Scan TCK Input Timing TCK tTRSS tTRSS TRST tTRSW Figure 27.22 Boundary Scan TRST Input Timing (At Reset Hold) REJ09B0140-0900 Rev. 9.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) TCK tTDIS tTDIH tTMSS tTMSH TDI TMS tTDOD tTDOD TDO Figure 27.23 Boundary Scan Data Transmission Timing Page 828 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group 27.5 Section 27 Electrical Characteristics (H8S/2215C) USB Characteristics Table 27.8 lists the USB characteristics (USD+ and USD- pins) when the on-chip USB transceiver is used. Table 27.8 USB Characteristics (USD+ and USD- pins) when On-Chip USB Transceiver Is Used Condition: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 16 MHz to 24 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (widerange specifications) Item Symbol Min. Max.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) Rise Time USD+, USD- Fall Time 90% VCRS 90% 10% Differential Date Lines 10% tR tF Figure 27.24 Data Signal Timing USD+ Rs = 24 Ω Test Point CL = 50 pF USD- Rs = 24 Ω Test Point CL = 50 pF Figure 27.25 Test Load Circuit Page 830 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group 27.6 Section 27 Electrical Characteristics (H8S/2215C) A/D Conversion Characteristics Table 27.9 lists the A/D conversion characteristics. Table 27.9 A/D Conversion Characteristics Condition: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V*, AVCC = 3.0 V to 3.6 V*, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, φ = 16 MHz to 24 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Min. Typ. Max.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) 27.8 Flash Memory Characteristics Table 27.11 Flash Memory Characteristics Condition: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) 2. Programming time per 128 bytes (Shows the total period for which the P-bit in the flash memory control register (FLMCR1) is set. It does not include the programming verification time). 3. Block erase time (Shows the total period for which the E1-bit FLMCR1 is set. It does not include the erase verification time). 4. Maximum programming time value tp (max.
H8S/2215 Group Section 27 Electrical Characteristics (H8S/2215C) 27.9 Usage Note General Notice during Design for Printed Circuit Board: Measures for radiation noise caused by the transient current in this LSI should be taken into consideration. The examples of the measures are shown below. • To use a multilayer printed circuit board which includes layers for Vcc and GND. • To mount by-pass capacitors (approximately 0.1 μF) between the Vcc and GND (Vss) pins, and the PLLVCC and PLLGND pins, of this LSI.
H8S/2215 Group Appendix Appendix A.
H8S/2215 Group Appendix Port Name Pin Name MCU Operating Mode Power-on Reset Manual Reset Hardware Standby Mode Software Standby Mode Bus Right Release State Program Execution State or Sleep Mode Port B 7 T keep T keep keep I/O port Address output selected by AEn bit 4 and 5 L keep T [OPE=0] T Address output 6 T Port selection 4 to 6 T* keep T keep keep I/O port 4 and 5 L keep T [OPE=0] T Address output T [OPE=1] keep Port C T [OPE=1] keep 6 T keep T [DDR•OPE
H8S/2215 Group Appendix Port Name Pin Name MCU Operating Mode Power-on Reset Manual Reset Hardware Standby Mode Software Standby Mode Bus Right Release State Program Execution State or Sleep Mode PF3/LWR I/O port 7 T keep T keep keep 8-bit bus 4 to 6 (Mode 4) keep T keep keep I/O port 16-bit bus 4 to 6 H H T [OPE=0] T LWR [WAITE=0] [WAITE=0] [WAITE=0] keep keep I/O port [WAITE=1] [WAITE=1] [WAITE=1] T T WAIT (Modes 5 ,6) T T [OPE=1] H PF2/WAIT PF1/BACK 4 t
H8S/2215 Group Appendix Legend: H: High level L: Low level T: High impedance keep: Input port level is high impedance, and output port level is retained. DDR: Data direction register OPE: Output port enable WAITE: Wait port enable BRLE: Bus release enable Note: * L (address input) in mode 4 or 5 Page 838 of 846 REJ09B0140-0900 Rev. 9.
H8S/2215 Group B. Appendix Product Model Lineup Product Class Part No.
H8S/2215 Group Appendix C. Package Dimensions The package dimension that is shown in the Renesas Semiconductor Package Data Book has Priority. JEITA Package Code P-TQFP120-14x14-0.40 RENESAS Code PTQP0120LA-A Previous Code TFP-120/TFP-120V MASS[Typ.] 0.5g HD *1 D 90 61 91 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
H8S/2215 Group Appendix JEITA Package Code P-LFBGA112-10x10-0.80 RENESAS Code PLBG0112GA-A Previous Code BP-112/BP-112V MASS[Typ.] 0.3g D w S B E w S A ×4 v y1 S y A1 A S S ZD e A L K e J Reference Symbol H B G Dimension in Millimeters Min Nom Max D 10.00 F E 10.00 E v D w 0.20 A 1.40 ZE C B A1 0.15 0.35 e A b 1 2 3 4 5 φ b 6 7 φ 8 9 ×M S A B 10 11 0.40 0.45 0.80 0.45 0.50 0.55 x 0.08 y 0.10 y1 0.2 SD SE ZD 1.00 ZE 1.00 Figure C.
Appendix Page 842 of 846 H8S/2215 Group REJ09B0140-0900 Rev. 9.
Index Index 16-Bit Timer Pulse Unit.......................... 283 Buffer Operation................................. 320 Free-running count operation.............. 314 Input Capture Function ....................... 317 periodic count operation ..................... 314 Phase Counting Mode......................... 328 PWM Modes....................................... 324 Synchronous Operation....................... 319 toggle output .......................................
Index Hardware Protection ........................... 656 Program/Program-Verify.................... 652 Programmer Mode.............................. 657 programming units.............................. 633 Programming/Erasing in User Program Mode................................................... 649 Software Protection ............................ 656 Framing error.......................................... 430 General Registers...................................... 32 Instruction Set.....................
Index LPWRCR............................ 670, 711, 720 MAR ................................... 153, 712, 721 MDCR .................................. 64, 711, 719 MRA ................................... 208, 710, 719 MRB ................................... 209, 710, 719 MSTPCR ............................ 686, 711, 719 MSTPCRB.......................................... 543 P1DDR................................ 233, 711, 720 P1DR .................................. 234, 713, 722 P3DDR..........................
Index UEDR0o ............................. 514, 709, 718 UEDR0s.............................. 513, 709, 718 UEDR1i .............................. 514, 709, 718 UEDR2i .............................. 515, 709, 718 UEDR2o ............................. 515, 709, 718 UEDR3i .............................. 515, 709, 718 UEDR3o ............................. 516, 709, 718 UEDR4i .............................. 516, 709, 718 UEDR4o ............................. 516, 709, 718 UEDR5i ..............................
Renesas 16-Bit Single-Chip Microcomputer H8S/2215 Group User's Manual: Hardware Publication Date: Rev.1.00, April, 2001 Rev.9.
http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada Tel: +1-905-898-5441, Fax: +1-905-898-3220 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.
H8S/2215 Group User's Manual: Hardware REJ09B0140-0900
