Datasheet

Section 6 Bus Controller
REJ09B0140-0900 Rev. 9.00 Page 111 of 846
Sep 16, 2010
H8S/2215 Group
6.2 Input/Output Pins
Table 6.1 summarizes the pins of the bus controller.
Table 6.1 Pin Configuration
Name Symbol I/O Function
Address strove AS Output Strobe signal indicating that address output on
address bus is enabled.
Read RD Output Strobe signal indicating that external space is being
read.
High write HWR Output Strobe signal indicating that external space is to be
written, and upper half (D15 to D8) of data bus is
enabled.
Low write LWR Output Strobe signal indicating that external space is to be
written, and lower half (D7 to D0) of data bus is
enabled.
Chip select 0 to 7 CS0 to CS7 Output Strobe signal indicating that areas 0 to 7 are selected.
Wait WAIT Input Wait request signal when accessing external 3-state
access space.
Bus request BREQ Input Request signal that releases bus to external device.
Bus request
acknowledge
BACK Output Acknowledge signal indicating that bus has been
released.
6.3 Register Descriptions
The following shows the registers of the bus controller.
• Bus width control register (ABWCR)
• Access state control register (ASTCR)
• Wait control register H (WCRH)
• Wait control register L (WCRL)
• Bus control register H (BCRH)
• Bus control register L (BCRL )
• Pin function control register (PFCR)