Datasheet

Section 12 8-Bit Timers
Rev. 6.00 Mar. 18, 2010 Page 453 of 982
REJ09B0054-0600
TCNT
H'FF
Counter clear
TCORA
TCORB
H'00
TMO
Figure 12.2 Example of Pulse Output
12.5 Operation Timing
12.5.1 TCNT Incrementation Timing
Figure 12.3 shows the TCNT count timing with internal clock source. Figure 12.4 shows the
TCNT incrementation timing with external clock source. The pulse width of the external clock for
incrementation at signal edge must be at least 1.5 system clock (φ) periods, and at least 2.5 states
for incrementation at both edges. The counter will not increment correctly if the pulse width is less
than these values.
φ
Internal clock
TCNT input
clock
TCNT
N − 1 N N + 1
Figure 12.3 Count Timing for Internal Clock Input