Datasheet

Section 15 Serial Communication Interface (SCI)

Rev. 6.00 Mar. 18, 2010 Page 626 of 982

REJ09B0054-0600

15.10.5 Restrictions on Use of DMAC* or DTC

• When an external clock source is used as the serial clock, the transmit clock should not be

input until at least 5 φ clock cycles after the TDR is updated by the DMAC* or the DTC.

Misoperation may occur if the transmit clock is input within 4 φ clocks after TDR is updated

(figure 15.38).

• When RDR is read by the DMAC* or the DTC, be sure to set the activation source to the

relevant SCI reception data full interrupt (RXI).

• The flag is cleared only when DISEL in DTC is 0 with the transfer counter not being 0. When

DISEL is 1, or DISEL is 0 with the transfer counter being 0, the flag should be cleared by

CPU. Note that transmitting, in particular, may not successfully be executed unless the TDRE

flag is cleared by CPU.

Note: * Supported only by the H8S/2239 Group.

LSB

Serial data

SCK

D3 D4 D5D2 D6 D7

Note: When operating on an external clock, set t > 4 clocks.

TDRE

Figure 15.38 Example of Clocked Synchronous Transmission by DMAC* or DTC

Note: * Supported only by the H8S/2239 Group.

15.10.6 Operation in Case of Mode Transition

• Transmission

Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module

stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition.

TSR, TDR, and SSR are reset. The output pin states in module stop mode, software standby

mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and

becomes high-level output after the relevant mode is cleared. If a transition is made during

transmission, the data being transmitted will be undefined. When transmitting without

changing the transmit mode after the relevant mode is cleared, transmission can be started by

setting TE to 1 again, and performing the following sequence: SSR read → TDR write →