Datasheet

Section 16 I
2
C Bus Interface (IIC) (Option)
Rev. 6.00 Mar. 18, 2010 Page 636 of 982
REJ09B0054-0600
SCL
in
SCL
out
SDA
in
SDA
out
(Slave 1)
SCL SDA
SCL
in
SCL
out
SDA
in
SDA
out
(Slave 2)
SCL SDA
SCL
in
SCL
out
SDA
in
SDA
out
(Master)
This LSI
SCL
SDA
V
DD
V
CC
SCL
SDA
Figure 16.2 I
2
C Bus Interface Connections (Example: This LSI as Master)
16.2 Input/Output Pins
Table 16.1 shows the pin configuration for the I
2
C bus interface.
Table 16.1 Pin Configuration
Name Abbreviation
*
I/O Function
Serial clock SCL0 I/O IIC_0 serial clock input/output
Serial data SDA0 I/O IIC_0 serial data input/output
Serial clock SCL1 I/O IIC_1 serial clock input/output
Serial data SDA1 I/O IIC_1 serial data input/output
Note: * Pin names SCL and SDA are used in the text for all channels, omitting the channel
designation.
16.3 Register Descriptions
The I
2
C bus interface has the following registers. Registers ICDR and SARX and registers ICMR
and SAR are allocated to the same addresses. Accessible addresses differ depending on the ICE bit
in ICCR. SAR and SARX are accessed when ICE is 0, and ICMR and ICDR are accessed when