Datasheet

Section 27 Electrical Characteristics
Rev. 6.00 Mar. 18, 2010 Page 901 of 982
REJ09B0054-0600
(4) Timing of On-Chip Peripheral Modules
Table 27.33 shows the timing of on-chip peripheral modules, and table 27.34 shows the I
2
C bus
timing.
Table 27.33 Timing of On-Chip Peripheral Modules
Condition A (F-ZTAT version): V
CC
= 3.0 V to 5.5 V, AV
CC
= 3.6 V to 5.5 V,
V
ref
= 3.6 V to AV
CC
, V
SS
= AV
SS
= 0 V,
φ = 32.768 kHz, 2 MHz to 13.5 MHz,
T
a
= –20°C to +75°C (regular specifications),
T
a
= –40°C to +85°C (wide-range specifications)
Condition B (Masked ROM version): V
CC
= 2.7 V to 5.5 V, AV
CC
= 3.6 V to 5.5 V,
V
ref
= 3.6 V to AV
CC
, V
SS
= AV
SS
= 0 V,
φ = 32.768 kHz, 2 MHz to 13.5 MHz,
T
a
= –20°C to +75°C (regular specifications),
T
a
= –40°C to +85°C (wide-range specifications)
Conditions A, B
Item Symbol Min Max Unit Test Conditions
I/O port
*
Output data delay time t
PWD
⎯ 100 ns Figure 27.24
Input data setup time t
PRS
50 ⎯
Input data hold time t
PRH
50 ⎯
TPU Timer output delay time t
TOCD
⎯ 100 ns Figure 27.25
Timer input setup time t
TICS
40 ⎯
Timer clock input setup time t
TCKS
40 ⎯ ns Figure 27.26
Single edge t
TCKWH
1.5 ⎯ t
cyc
Timer clock
pulse width
Both edges t
TCKWL
2.5 ⎯
TMR Timer output delay time t
TMOD
⎯ 100 ns Figure 27.27
Timer reset input setup time t
TMRS
50 ⎯ ns Figure 27.29
Timer clock input setup time t
TMCS
50 ⎯ ns Figure 27.28
Single edge t
TMCWH
1.5 ⎯ t
cyc
Timer clock
pulse width
Both edges t
TMCWL
2.5 ⎯