Datasheet

Appendix B Internal I/O Registers
Rev.7.00 Feb. 14, 2007 page 1001 of 1108
REJ09B0089-0700
PFCR1—Port Function Control Register 1 H'FF45 Port
7
CSS17
0
R/W
6
CSS36
0
R/W
5
PF1CS5S
0
R/W
4
PF0CS4S
0
R/W
3
A23E
1
R/W
0
A20E
1
R/W
2
A22E
1
R/W
1
A21E
1
R/W
Bit
Initial value
Read/Write
:
:
:
0
1
P10DR is output when P10DDR = 1
A20 is output when P10DDR = 1
Address 20 Output Enable
*1
0
1
P11DR is output when P11DDR = 1
A21 is output when P11DDR = 1
Address 21 Output Enable
*1
0
1
P12DR is output when P12DDR = 1
A22 is output when P12DDR = 1
Address 22 Output Enable
*1
0
1
PF0 is PF0/BREQ/IRQ0 pin
PF0 is PF0/BREQ/IRQ0/CS4 pin. CS4 output is enabled when
BRLE = 0, CS25E = 1, and PF0DDR = 1
Port F0 chip select 4 select
*1
0
1
PF1 is PF1/BACK/IRQ1 pin
PF1 is PF1/BACK/IRQ1/CS5 pin. CS5 output is enabled when BRLE = 0,
CS25E = 1, and PF1DDR = 1
Port F1 chip select 5 select
*1
0
1
PG1 is PG1/IRQ7/CS3 pin. CS3 output is enabled when when CS25E = 1 and PG1DDR = 1
PG1 is PG1/IRQ7/CS6 pin. CS6 output is enabled when CS167E = 1 and PG1DDR = 1
CS36 select
*1 *3
0
1
PG3 is PG3/CS1 pin. CS1 output is enabled when CS167E = 1 and PG3DDR = 1
PG3 is PG3/CS7 pin. CS7 output is enabled when CS167E = 1 and PG3DDR = 1
CS17 select
*1 *2
Notes: 1. Valid in modes 4 to 6.
2. Clear PG3DDR to 0 before changing the CSS17 bit setting.
3. Clear PG1DDR to 0 before changing the CSS36 bit setting.
0
1
P13DR is output when P13DDR = 1
A23 is output when P13DDR = 1
Address 23 Output Enable
*1