Datasheet

Appendix B Internal I/O Registers
Rev.7.00 Feb. 14, 2007 page 1050 of 1108
REJ09B0089-0700
TCR0—Timer Control Register 0 H'FFD0 TPU0
(Valid only in the H8S/2319C F-ZTAT)
7
CCLR2
0
R/W
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
0
TPSC0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel
Counter Clear
0
0
1
0
1
0
1
0
1
Clock Edge
0
1
⎯
Count at rising edge
Count at falling edge
Count at both edges
Internal clock: counts on φ/1
Internal clock: counts on φ/4
Internal clock: counts on φ/16
Internal clock: counts on φ/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
External clock: counts on TCLKC pin input
External clock: counts on TCLKD pin input
Time Prescaler
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Bit
Initial value
Read/Write
:
:
:
Notes: 1. Synchronous operation setting is performed by setting the
SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is
not cleared because the buffer register setting has priority,
and compare match/input capture does not occur.
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation
*
1
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation
*
1
10
1
0
1
0
1
TCNT clearing disabled
TCNT cleared by TGRC compare match/input capture
*
2
TCNT cleared by TGRD compare match/input capture
*
2
Note:
The internal clock edge selection is valid when the input clock is
φ/4 or slower. This setting is ignored if φ/1 or overflow/underflow
on another channel is selected as the input clock.