Datasheet

Appendix B Internal I/O Registers
Rev.7.00 Feb. 14, 2007 page 1058 of 1108
REJ09B0089-0700
TMDR1—Timer Mode Register 1 H'FFE1 TPU1
0
1
Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4
⎯
Mode
0
1
×
0
1
0
1
×
0
1
0
1
0
1
0
1
×
Note:
MD3 is a reserved bit. In a write, it
should always be written with 0.
× : Don't care
7
⎯
1
⎯
6
⎯
1
⎯
5
⎯
0
⎯
4
⎯
0
⎯
3
MD3
0
R/W
0
MD0
0
R/W
2
MD2
0
R/W
1
MD1
0
R/W
Bit
Initial value
Read/Write
:
:
: