Datasheet

Section 3 MCU Operating Modes
Rev.7.00 Feb. 14, 2007 page 76 of 1108
REJ09B0089-0700
Bit 2—LWR Output Disable (LWROD): Enables or disables LWR output.
Bit 2
LWROD Description
0 PF3 is designated as LWR output pin (Initial value)
1 PF3 is designated as I/O port, and does not function as LWR output pin
Bit 1—Reserved: Only 0 should be written to this bit.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled (Initial value)
3.2.3 System Control Register 2 (SYSCR2) (F-ZTAT Versions Only)
Bit : 7 6 5 4 3 2 1 0
— — — — FLSHE — — —
Initial value : 0 0 0 0 0 0 0 0
R/W : — — — — R/W — — — (R/W)
*
Note: * R/W in the H8S/2319 F-ZTAT.
SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control.
SYSCR2 is initialized to H'00 by a reset, and in hardware standby mode.
Bits 7 to 4—Reserved: These bits are always read as 0, and cannot be modified.
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2 in the case of the H8S/2319 F-
ZTAT, H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT;
FCCS, FPCS, FECS, FKEY, FMATS, FTDAR, FVARC, FVADRR, FVADRE, FVADRH, and
FVADRL in the case of the H8S/2319C F-ZTAT). For details, see section 17, ROM.