Datasheet

Appendix C I/O Port Block Diagrams
Rev.7.00 Feb. 14, 2007 page 1092 of 1108
REJ09B0089-0700
R
PG1DDR
C
QD
Reset
WDDRG
Reset
WDRG
R
PG1DR
C
QD
PG1
RDRG
RPORG
Bus controller
Chip select 3
Chip select 6
Port
CS167E bit
CS25E bit
CSS36 bit
Mode 7
Internal data bus
Modes
4 to 6
Legend:
WDDRG: Write to PGDDR
WDRG: Write to PGDR
RDRG: Read PGDR
RPORG: Read port G
CS25E: CS25 enable
CS167E: CS167 enable
CSS36: CS36 select
Figure C.11(b) Port G Block Diagram (Pin PG1)