Datasheet

Appendix C I/O Port Block Diagrams
Rev.7.00 Feb. 14, 2007 page 1095 of 1108
REJ09B0089-0700
QD
WDDRG
Reset
Reset
WDRG
R
PG4DR
C
QD
PG4
RDRG
RPORG
Bus controller
Chip select 0
Mode 7
Modes 4 to 6
Modes
4 and 5
Modes
6 and 7
D
SR
C
Q
PG4DDR
Internal data bus
Legend:
WDDRG: Write to PGDDR
WDRG: Write to PGDR
RDRG: Read PGDR
RPORG: Read port G
D
Figure C.11(e) Port G Block Diagram (Pin PG4)