Datasheet

Section 6 Bus Controller
Rev.7.00 Feb. 14, 2007 page 154 of 1108
REJ09B0089-0700
Table 6.3 Bus Specifications for Each Area (Basic Bus Interface)
WCRH, WCRL Bus Specifications (Basic Bus Interface)
ABWCR
ABWn
ASTCR
ASTn Wn1 Wn0 Bus Width Access States
Program Wait
States
0 0 — — 16 2 0
1 0 0 3 0
1 1
1 0 2
1 3
1 0 — — 8 2 0
1 0 0 3 0
1 1
1 0 2
1 3
6.3.3 Memory Interfaces
The chip’s memory interfaces comprise a basic bus interface that allows direct connection of
ROM, SRAM, and so on; and a burst ROM interface that allows direct connection of burst ROM.
The interface can be selected independently for each area.
An area for which the basic bus interface is designated functions as normal space, and an area for
which the burst ROM interface is designated functions as burst ROM space.