Section 6 Bus Controller
Rev.7.00 Feb. 14, 2007 page 171 of 1108
REJ09B0089-0700
T
1
ddress bus
φ
CS0
AS
Data bus
T
2
T
3
T
1
T
2
T
1
Full access
T
2
RD
Burst access
Only lower address changed
Read data Read data Read data
Figure 6.15 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1)
