Datasheet

Section 8 I/O Ports
Rev.7.00 Feb. 14, 2007 page 225 of 1108
REJ09B0089-0700
Port Function Control Register 1 (PFCR1)
Bit : 7 6 5 4 3 2 1 0
CSS17 CSS36 PF1CS5S PF0CS4S A23E A22E A21E A20E
Initial value : 0 0 0 0 1 1 1 1
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PFCR1 is an 8-bit readable/writable register that performs I/O port control. PFCR1 is initialized to
H'0F by a reset, and in hardware standby mode.
Bit 7—CS17 Select (CSS17): Selects whether CS1 or CS7 is output from the PG3 pin. For
details, see section 8.12, Port G.
Bit 6—CS36 Select (CSS36): Selects whether CS3 or CS6 is output from the PG1 pin. For
details, see section 8.12, Port G.
Bit 5—Port F1 Chip Select 5 Select (PF1CS5S): Selects enabling or disabling of CS5 output.
For details, see section 8.11, Port F.
Bit 4—Port F0 Chip Select 4 Select (PF0CS4S): Selects enabling or disabling of CS4 output.
For details, see section 8.11, Port F.
Bit 3—Address 23 Enable (A23E): Enables or disables address output 23 (A23). This bit is valid
in modes 4 to 6.
Bit 3
A23E Description
0 P13DR is output when P13DDR = 1
1 A23 is output when P13DDR = 1 (Initial value)
Bit 2—Address 22 Enable (A22E): Enables or disables address output 22 (A22). This bit is valid
in modes 4 to 6.
Bit 2
A22E Description
0 P12DR is output when P12DDR = 1
1 A22 is output when P12DDR = 1 (Initial value)