Datasheet

Section 9 16-Bit Timer Pulse Unit (TPU)
Rev.7.00 Feb. 14, 2007 page 341 of 1108
REJ09B0089-0700
Examples of 8-bit register access operation are shown in figures 9.3 to 9.5.
Bus interface
H
Internal data bus
L
Module
data bus
TCR
Bus
master
Figure 9.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)]
Bus interface
H
Internal data bus
L
Module
data bus
TMDR
Bus
master
Figure 9.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)]
Bus interface
H
Internal data bus
L
Module
data bus
TCR TMDR
Bus
master
Figure 9.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)]