Datasheet

Section 9 16-Bit Timer Pulse Unit (TPU)
Rev.7.00 Feb. 14, 2007 page 379 of 1108
REJ09B0089-0700
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC is activated, the flag is cleared automatically. Figure 9.46 shows the timing
for status flag clearing by the CPU, and figure 9.47 shows the timing for status flag clearing by the
DTC.
Status flag
Write signal
A
ddress
φ
TSR address
Interrupt
request
signal
TSR write cycle
T
1
T
2
Figure 9.46 Timing for Status Flag Clearing by CPU
Interrupt
request
signal
Status flag
A
ddress
φ
Source address
DTC
read cycle
T
1
T
2
Destination
address
T
1
T
2
DTC
write cycle
Figure 9.47 Timing for Status Flag Clearing by DTC Activation