Datasheet

Section 1 Overview
Rev.7.00 Feb. 14, 2007 page 8 of 1108
REJ09B0089-0700
1.2 Block Diagram
PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0
Internal data bus
Peripheral data bus Peripheral address bus
PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8
Port D
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
Port
A
PA3/A19
PA2/A18
PA1/A17
PA0/A16
PB7/A15
PB6/A14
PB5/A13
PB4/A12
PB3/ A11
PB2/A10
PB1/A9
PB0/A8
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
Port
B
Port
C
Port
3
P35/SCK1/IRQ
5
P34/SCK0/IRQ
4
P33/RxD1
P32/RxD0
P31/TxD1
P30/TxD0
P47/AN7/DA1 P46/AN6/DA0 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0
V
ref
AV
CC
AV
SS
P20/TIOCA3 P21/TIOCB3 P22/TIOCC3/TMRI0 P23/TIOCD3/TMCI0 P24/TIOCA4/TMRI1 P25/TIOCB4/TMCI1 P26/TIOCA5/TMO0 P27/TIOCB5/TMO1
P10/TIOCA0/A20 P11/TIOCB0/A21 P12/TIOCC0/TCLKA/A22 P13/TIOCD0/TCLKB/A23 P14/TIOCA1 P15/TIOCB1/TCLKC P16/TIOCA2 P17/TIOCB2/TCLKD
PG4/CS0
PG3/CS1/CS7
PG2/CS2
PG1/CS3/IRQ7/CS6
PG0/ADTRG/IRQ6
Port
G
PF7/φ
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR/IRQ3
PF2/WAIT/IRQ2/DREQO
PF1/BACK/IRQ1/CS5
PF0/BREQ/IRQ0/CS4
Port
F
Clock pulse
generator
ROM
*
2
RAM
TPU
SCI
MD2
MD1
MD0
EXTAL
XTAL
STBY
RES
WDTOVF (FWE, EMLE, V
CL
)
*
1
NMI
H8S/2000 CPU
DTC
Interrupt controller
Port E
Port 4Port 2Port 1
Internal address bus
WDT
8-bit timer
D/A converter
A/D converter
Bus controller
Notes: 1. The FWE pin function is only available in the H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT,
and H8S/2314 F-ZTAT.
The EMLE pin function is only available in the H8S/2319 F-ZTAT.
The V
CL
pin function is only available in the H8S/2319C F-ZTAT.
The WDTOVF pin function is not available in the F-ZTAT versions.
2. ROM is not supported in the ROMless versions.
Figure 1.1 Block Diagram