Datasheet

Section 10 8-Bit Timers
Rev.7.00 Feb. 14, 2007 page 408 of 1108
REJ09B0089-0700
10.6 Usage Notes
Note that the following kinds of contention can occur in the 8-bit timer module.
10.6.1 Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T
2
state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed.
Figure 10.10 shows this operation.
φ
A
ddress TCNT address
Internal write signal
Counter clear signal
TCNT
N H'00
T
1
T
2
TCNT write cycle by CPU
Figure 10.10 Contention between TCNT Write and Clear