Datasheet

Section 12 Serial Communication Interface (SCI)

Rev.7.00 Feb. 14, 2007 page 494 of 1108

REJ09B0089-0700

Restrictions on Use of DTC

• When an external clock source is used as the serial clock, the transmit clock should not be

input until at least 5 φ clock cycles after TDR is updated by the DTC. Misoperation may occur

if the transmit clock is input within 4 φ clocks after TDR is updated. (Figure 12.22)

• When RDR is read by the DTC, be sure to set the activation source to the relevant SCI receive-

data-full interrupt (RXI).

LSB

Serial data

SCK

D3 D4 D5D2 D6 D7

Note: When operating on an external clock, set t > 4 clocks.

TDRE

Figure 12.22 Example of Synchronous Transmission Using DTC

Operation in Case of Mode Transition

• Transmission

Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module

stop mode or software standby mode transition. TSR, TDR, and SSR are reset. The output pin

states in module stop mode or software standby mode depend on the port settings, and

becomes high-level output after the relevant mode is cleared. If a transition is made during

transmission, the data being transmitted will be undefined. When transmitting without

changing the transmit mode after the relevant mode is cleared, transmission can be started by

setting TE to 1 again, and performing the following sequence: SSR read → TDR write →

TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode,

the procedure must be started again from initialization. Figure 12.23 shows a sample flowchart

for mode transition during transmission. Port pin states are shown in figures 12.24 and 12.25.

Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a

transition from transmission by DTC transfer to module stop mode or software standby mode

transition. To perform transmission with the DTC after the relevant mode is cleared, setting

TE and TIE to 1 will set the TXI flag and start DTC transmission.