Datasheet

Section 13 Smart Card Interface
Rev.7.00 Feb. 14, 2007 page 527 of 1108
REJ09B0089-0700
Internal
base
clock
372 clocks
186 clocks
Receive
data (RxD)
Synchro-
nization
sampling
timing
D0 D1
Data
sampling
timing
185
371 0
371
185
0
0
Start bit
Figure 13.10 Receive Data Sampling Timing in Smart Card Mode
(When Using 372-Times Clock)
Thus the receive margin in asynchronous mode is given by the following formula.
M =⎥ (0.5 –
1
2N
) – (L – 0.5) F –
⎥ D – 0.5⎥
N
(1 + F)⎥ × 100%
Where M: Receive margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, 256)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Assuming values of F = 0, D = 0.5, and N=372 in the above formula, the receive margin formula
is as follows.
When D = 0.5 and F = 0,
M = (0.5 – 1/2 × 372) × 100%
= 49.866%