Datasheet

Section 17 ROM
Rev.7.00 Feb. 14, 2007 page 646 of 1108
REJ09B0089-0700
17.14.4 Erase Block Register 2 (EBR2)
Bit : 7 6 5 4 3 2 1 0
EBR2 EB15 EB14 EB13 EB12 EB11 EB10 EB9 EB8
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, and when the
SWE1 bit in FLMCR1 is not set. When a bit in EBR2 is set, the corresponding block can be
erased. Other blocks are erase-protected. Set only one bit in EBR2 and EBR1 together (setting
more than one bit will automatically clear all EBR1 and EBR2 bits to 0). When on-chip flash
memory is disabled, a read will return H'00, and writes are invalid.
The flash memory block configuration is shown in table 17.28.
Table 17.28 Flash Memory Erase Blocks
Block (Size) Address
EB0 (4 kbytes) H'000000 to H'000FFF
EB1 (4 kbytes) H'001000 to H'001FFF
EB2 (4 kbytes) H'002000 to H'002FFF
EB3 (4 kbytes) H'003000 to H'003FFF
EB4 (4 kbytes) H'004000 to H'004FFF
EB5 (4 kbytes) H'005000 to H'005FFF
EB6 (4 kbytes) H'006000 to H'006FFF
EB7 (4 kbytes) H'007000 to H'007FFF
EB8 (32 kbytes) H'008000 to H'00FFFF
EB9 (64 kbytes) H'010000 to H'01FFFF
EB10 (64 kbytes) H'020000 to H'02FFFF
EB11 (64 kbytes) H'030000 to H'03FFFF
EB12 (64 kbytes) H'040000 to H'04FFFF
EB13 (64 kbytes) H'050000 to H'05FFFF
EB14 (64 kbytes) H'060000 to H'06FFFF
EB15 (64 kbytes) H'070000 to H'07FFFF