Datasheet

Section 17 ROM
Rev.7.00 Feb. 14, 2007 page 696 of 1108
REJ09B0089-0700
There are two memory MATs: user MAT and user boot MAT. The dedicated registers/parameters
are allocated for each operating mode and MAT selection. The correspondence of operating modes
and registers/parameters for use is shown in table 17.49.
Table 17.48 (1) Register Configuration
Name Abbreviation R/W Initial Value Address
Flash code control status register FCCS R, W
*
1
H'00
H'80
H'FFC4
Flash program code select register FPCS R/W H'00 H'FFC5
Flash erase code select register FECS R/W H'00 H'FFC6
Flash key code register FKEY R/W H'00 H'FFC8
Flash MAT select register FMATS R/W H'00
*
2
H'AA
*
2
H'FFC9
Flash transfer destination address
register
FTDAR R/W H'00 H'FFCA
System control register 2 SYSCR2
*
3
R/W H'00 H'FF42
RAM emulation register RAMER R/W H'00 H'FEDB
Notes: 1. The bits except the SCO bit are read-only bits. The SCO bit is a programming-only bit.
(The value which can be read is always 0.)
2. The initial value at initiation in user mode or user program mode is H'00.
The initial value at initiation in user boot mode is H'AA.
3. SYSCR2 is dedicated to the F-ZTAT versions.
Table 17.48 (2) Parameter Configuration
Name Abbreviation R/W Initial Value Address
Download pass/fail result DPFR R/W Undefined On-chip RAM
*
Flash pass/fail result FPFR R/W Undefined R0L of CPU
Flash multipurpose address area FMPAR R/W Undefined ER1 of CPU
Flash multipurpose data destination
area
FMPDR R/W Undefined ER0 of CPU
Flash erase block select FEBS R/W Undefined ER0 of CPU
Flash program and erase frequency
control
FPEFEQ R/W Undefined ER0 of CPU
Note: * One byte of the start address in the on-chip RAM area specified by FTDAR is valid.