Datasheet

Section 17 ROM
Rev.7.00 Feb. 14, 2007 page 697 of 1108
REJ09B0089-0700
Table 17.49 Register/Parameter and Target Mode
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Initiali-
zation
Program-
ming Erasure Read
RAM
Emulation
FCCS
— — — — —
FPCS — — — — —
PECS — — — — —
FKEY — — —
Programming/
erasing interface
registers
FMATS — —
*
1
*
1
*
2
—
FPFR — —
FPEFEQ — — — — —
FMPAR — — — — —
FMPDR — — — — —
Programming/
erasing interface
parameter
FEBS — — —
— —
RAM emulation RAMER — — — — —
Notes: 1. The setting is required when programming or erasing user MAT in user boot mode.
2. The setting may be required according to the combination of initiation mode and read
target MAT.
17.23 Register Description of Flash Memory
17.23.1 Programming/Erasing Interface Register
The programming/erasing interface registers are as described below. They are all 8-bit registers
that can be accessed in byte. Except for the FLER bit in FCCS, these registers are initialized at a
power-on reset, in hardware standby mode, or in software standby mode. The FLER bit is not
initialized in software standby mode.