Datasheet

Section 2 CPU
Rev.7.00 Feb. 14, 2007 page 43 of 1108
REJ09B0089-0700
2.6.2 Instructions and Addressing Modes
Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU
can use.
Table 2.2 Combinations of Instructions and Addressing Modes
Addressing Modes
Function
Data
transfer
Arithmetic
operations
Instruction
#xx Rn @ERn @(d:16,ERn) @(d:32,ERn) @−ERn/@ERn+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,PC) @(d:16,PC) @@aa:8
⎯
Logic
operations
System
control
Block data transfer
Shift
Bit manipulation
Branch
Legend:
Size refers to the operand size.
B: Byte
W: Word
L: Longword
Notes: 1. Cannot be used in the H8S/2319 Group.
2. Only register ER0, ER1, ER4, or ER5
should be used when using the TAS instruction.
MOV BWL BWL BWL BWL BWL BWL B BWL ⎯ BWL ⎯ ⎯ ⎯ ⎯
POP, PUSH ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ WL
LDM, STM ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ L
MOVFPE, ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ B ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
MOVTPE
*
1
ADD, CMP BWL BWL ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
SUB WL BWL ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
ADDX, SUBX B B ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
ADDS, S
UBS ⎯ L ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
INC, DEC ⎯ BWL ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
DAA, DAS ⎯ B ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
MULXU, ⎯ BW ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
DIVXU
MULXS, ⎯ BW ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
DIVXS
NEG ⎯ BWL ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
EXTU, EXTS ⎯ WL ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
TAS
*
2
⎯ ⎯ B ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
AND, OR, BWL BWL ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
XOR
NOT ⎯ BWL ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
⎯ BWL ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
⎯ B B ⎯ ⎯ ⎯ B B ⎯ B ⎯ ⎯ ⎯ ⎯
Bcc, BSR ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
JMP, JSR ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
RT
S ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
TRAPA ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
RTE ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
SLEEP ⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
LDC B B W W W W ⎯ W ⎯ W ⎯ ⎯ ⎯ ⎯
STC ⎯ B W W W W ⎯ W ⎯ W ⎯ ⎯ ⎯ ⎯
ANDC, B ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯
ORC, XORC
NOP ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ BW