Datasheet

Section 18 Clock Pulse Generator
Rev.7.00 Feb. 14, 2007 page 799 of 1108
REJ09B0089-0700
External Clock: The external clock signal should have the same frequency as the system clock
(φ).
Table 18.4 and figure 18.6 show the input conditions for the external clock.
Table 18.4 External Clock Input Conditions
V
CC
= 2.7 V
to 3.3 V
V
CC
= 3.0 V
to 3.6 V
Item Symbol Min Max Min Max Unit
Test
Conditions
External clock input
low pulse width
t
EXL
20 — 10 — ns
External clock input
high pulse width
t
EXH
20 — 10 — ns
External clock rise time t
EXr
— 5 — 5 ns
External clock fall time t
EXf
— 5 — 5 ns
Figure 18.6
0.4 0.6 0.4 0.6 t
cyc
φ ≥ 5 MHz Clock low pulse width
level
t
CL
80 — 80 — ns φ < 5 MHz
0.4 0.6 0.4 0.6 t
cyc
φ ≥ 5 MHz Clock high pulse width
level
t
CH
80 — 80 — ns φ < 5 MHz
Figure 20.2
t
EXH
t
EXL
t
EXr
t
EXf
V
CC
× 0.5
EXTAL
Figure 18.6 External Clock Input Timing