Datasheet

Section 20 Electrical Characteristics
Rev.7.00 Feb. 14, 2007 page 825 of 1108
REJ09B0089-0700
(3) Bus Timing
Table 20.6 Bus Timing
Condition A: V
CC
= 2.7 V to 3.6 V, AV
CC
= 2.7 V to 3.6 V, V
ref
= 2.7 V to AV
CC
, V
SS
= AV
SS
=
0 V, φ = 2 MHz to 20 MHz, T
a
= –20°C to 75°C (regular specifications),
T
a
= –40°C to 85°C (wide-range specifications)
Condition B: V
CC
= 3.0 V to 3.6 V, AV
CC
= 3.0 V to 3.6 V, V
ref
= 3.0 V to AV
CC
, V
SS
= AV
SS
=
0 V, φ = 2 MHz to 25 MHz, T
a
= –20°C to 75°C (regular specifications),
T
a
= –40°C to 85°C (wide-range specifications)
Condition A Condition B
Item Symbol Min Max Min Max Unit Test Conditions
Address delay time t
AD
— 20 — 20 ns Figures 20.6 to 20.10
Address setup time t
AS
0.5 ×
t
cyc
– 15
— 0.5 ×
t
cyc
– 15
— ns
Address hold time t
AH
0.5 ×
t
cyc
– 10
— 0.5 ×
t
cyc
– 8
— ns
CS delay time 1 t
CSD1
— 20 — 15 ns
AS delay time t
ASD
— 20 — 15 ns
RD delay time 1 t
RSD1
— 20 — 15 ns
RD delay time 2 t
RSD2
— 20 — 15 ns
Read data setup time t
RDS
15 — 15 — ns
Read data hold time t
RDH
0 — 0 — ns
Read data access
time 1
t
ACC1
— 1.0 ×
t
cyc
– 25
— 1.0 ×
t
cyc
– 20
ns
Read data access
time 2
t
ACC2
— 1.5 ×
t
cyc
– 25
— 1.5 ×
t
cyc
– 20
ns
Read data access
time 3
t
ACC3
— 2.0 ×
t
cyc
– 25
— 2.0 ×
t
cyc
– 20
ns
Read data access
time 4
t
ACC4
— 2.5 ×
t
cyc
– 25
— 2.5 ×
t
cyc
– 20
ns
Read data access
time 5
t
ACC5
— 3.0 ×
t
cyc
– 25
— 3.0 ×
t
cyc
– 20
ns