Datasheet

Section 20 Electrical Characteristics
Rev.7.00 Feb. 14, 2007 page 834 of 1108
REJ09B0089-0700
Condition A Condition B
Item Symbol Min Max Min Max Unit
Test
Conditions
SCI Asynchronous 4 — 4 — t
cyc
Figure 20.20
Input clock
cycle
Synchronous
t
Scyc
6 — 6 —
Input clock pulse width t
SCKW
0.4 0.6 0.4 0.6 t
Scyc
Input clock rise time t
SCKr
— 1.5 — 1.5 t
cyc
Input clock fall time t
SCKf
— 1.5 — 1.5 t
cyc
Transmit data delay time t
TXD
— 50 — 40 ns Figure 20.21
Receive data setup time
(synchronous)
t
RXS
50 — 40 — ns
Receive data hold time
(synchronous)
t
RXH
50 — 40 — ns
A/D
converter
Trigger input setup time t
TRGS
30 — 30 — ns Figure 20.22
φ
Ports 1 to 4,
A
to G
(read)
t
PRS
T
1
T
2
t
PWD
t
PRH
Ports 1 to 3,
A
to G
(write)
Figure 20.13 I/O Port Input/Output Timing