Datasheet

Section 20 Electrical Characteristics
Rev.7.00 Feb. 14, 2007 page 858 of 1108
REJ09B0089-0700
(4) Timing of On-Chip Supporting Modules
Table 20.26 Timing of On-Chip Supporting Modules
Condition B: V
CC
= 3.0 V to 3.6 V, AV
CC
= 3.0 V to 3.6 V, V
ref
= 3.0 V to AV
CC
, V
SS
= AV
SS
=
0 V, φ = 2 MHz to 25 MHz, T
a
= –20°C to 75°C (regular specifications),
T
a
= –40°C to 85°C (wide-range specifications)
Item Symbol Min Max Unit Test Conditions
Output data delay time t
PWD
— 40 ns
Input data setup time t
PRS
25 — ns
I/O ports
Input data hold time t
PRH
25 — ns
Figure 20.13
Timer output delay time t
TOCD
— 40 ns
Timer input setup time t
TICS
25 — ns
Figure 20.14
Timer clock input setup time t
TCKS
25 — ns
Single-edge
specification
t
TCKWH
1.5 — t
cyc
TPU
Timer clock
pulse width
Both-edge
specification
t
TCKWL
2.5 — t
cyc
Figure 20.15
Timer output delay time t
TMOD
— 40 ns Figure 20.16
Timer reset input setup time t
TMRS
25 — ns Figure 20.18
Timer clock input setup time t
TMCS
25 — ns
Single-edge
specification
t
TMCWH
1.5 — t
cyc
8-bit timer
Timer clock
pulse width
Both-edge
specification
t
TMCWL
2.5 — t
cyc
Figure 20.17
Asynchronous 4 — t
cyc
Input clock
cycle
Synchronous
t
Scyc
6 — t
cyc
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rise time t
SCKr
— 1.5 t
cyc
Input clock fall time t
SCKf
— 1.5 t
cyc
Figure 20.20
Transmit data delay time t
TXD
— 40 ns
Receive data setup time
(synchronous)
t
RXS
40 — ns
SCI
Receive data hold time
(synchronous)
t
RXH
40 — ns
Figure 20.21
A/D
converter
Trigger input setup time t
TRGS
30 — ns Figure 20.22