Datasheet

Section 2 CPU
Rev.7.00 Feb. 14, 2007 page 59 of 1108
REJ09B0089-0700
Table 2.6 Effective Address Calculation
Register indirect with post-increment or pre-decrement · Register indirect with post-increment @ERn+
No.Addressing Mode and Instruction Format
Effective Address Calculation
Effective Address (EA)
1 Register direct (Rn)
op rm rn
Operand is general register contents.
Register indirect (@ERn)2
Register indirect with displacement @(d:16, ERn)
or @(d:32, ERn)
3
· Register indirect with pre-decrement @−ERn
4
General register contents
General register contents
Sign extension
disp
General register contents
1, 2, or 4
General register contents
1, 2, or 4
Byte Word Longword
1 2 4
Operand Size Value
added
31 0 31 0 31 0 31 0 31
0 31 0
31 0 31 0 31 0
op
r r
op
op r
rop
disp
24 23
Don't care
24 23
Don't care
24 23
Don't care
24 23
Don't care