Datasheet

Appendix A Instruction Set
Rev.7.00 Feb. 14, 2007 page 932 of 1108
REJ09B0089-0700
Instruction
STC EXR,@(d:16,ERd)
R:W 2nd R:W 3rd R:W NEXT W:W EA
STC CCR,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA STC EXR,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA STC CCR,@−ERd R:W 2nd R:W NEXT
Internal operation,
W:W EA
1 state
STC EXR,@−ERd R:W 2nd R:W NEXT
Internal operation,
W:W EA
1 state
STC CCR,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W EA STC EXR,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W EA STC CCR,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA STC EXR,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA STM.L(ERn
−
ERn+1),@
−
SP
R:W 2nd R:W:M NEXT
Internal operation,
W:W:M stack (H)
*
3
W:W stack (L)
*
3
1 state
STM.L(ERn
−
ERn+2),@
−
SP
R:W 2nd R:W:M NEXT
Internal operation,
W:W:M stack (H)
*
3
W:W stack (L)
*
3
1 state
STM.L(ERn
−
ERn+3),@
−
SP
R:W 2nd R:W:M NEXT
Internal operation,
W:W:M stack (H)
*
3
W:W stack (L)
*
3
1 state
STMAC MACH,ERd Cannot be used in the chip STMAC MACL,ERd SUB.B Rs,Rd R:W NEXT SUB.W #xx:16,Rd R:W 2nd R:W NEXT SUB.W Rs,Rd R:W NEXT SUB.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT SUB.L ERs,ERd R:W NEXT SUBS #1/2/4,ERd R:W NEXT SUBX #xx:8,Rd R:W NEXT SUBX Rs,Rd R:W NEXT TAS @ERd
*
8
R:W 2nd R:W NEXT R:B:M EA W:B EA
TRAPA #x:2 R:W NEXT
Internal operation,
W:W stack (L) W:W stack (H) W:W stack (EXR)
R:W:M VEC R:W VEC+2
Internal operation,
R:W
*
7
1 state
1 state
XOR.B #xx8,Rd R:W NEXT XOR.B Rs,Rd R:W NEXT XOR.W #xx:16,Rd R:W 2nd R:W NEXT XOR.W Rs,Rd R:W NEXT XOR.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
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