Datasheet

Section 17 ROM
Rev.7.00 Feb. 14, 2007 page 567 of 1108
REJ09B0089-0700
17.2.2 Bus Control Register L (BCRL)
Bit : 7 6 5 4 3 2 1 0
BRLE BREQOE EAE — — — — WAITE
Initial value : 0 0 1 1 1 1 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
Enabling or disabling of part of the on-chip ROM area in the chip can be selected by means of the
EAE bit in BCRL. For details of the other bits in BCRL, see section 6.2.5, Bus Control Register L
(BCRL).
Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'03FFFF
*
2
are
to be internal addresses or external addresses.
Description
Bit 5
EAE
H8S/2319, H8S/2319C,
H8S/2318, H8S/2315,
H8S/2314
H8S/2317(S)
*
3
H8S/2316S
0 On-chip ROM Addresses H'010000 to H'01FFFF
are in on-chip ROM and addresses
H'020000 to H'03FFFF are a reserved
area
*
1
Reserved area
*
1
1 Addresses H'010000 to H'03FFFF
*
2
are external addresses (in external expanded
mode) or a reserved area
*
1
(in single-chip mode) (Initial value)
Notes: 1. The reserved area must not be accessed.
2. H'010000 to H'03FFFF in the H8S/2318.
H'010000 to H'05FFFF in the H8S/2315 and H8S/2314.
H'010000 to H'07FFFF in the H8S/2319 and H8S/2319C.
3. H8S/2317S in mask ROM version.
17.3 Operation
The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can
be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to
the lower 8 bits. Word data must start at an even address.
The on-chip ROM is enabled and disabled by setting the mode pins (MD2 to MD0) and the EAE
bit in BCRL. These settings are shown in table 17.2 and table 17.3.