Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Sep. 27, 2007 Page 470 of 1268
REJ09B0220-0600
10.2.4 Timer Interrupt Enable Registers (TIER)
Channel 0: TIER0
Channel 3: TIER3
Bit : 7 6 5 4 3 2 1 0
TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA
Initial value : 0 1 0 0 0 0 0 0
R/W : R/W — — R/W R/W R/W R/W R/W
Channel 1: TIER1
Channel 2: TIER2
Channel 4: TIER4
Channel 5: TIER5
Bit : 7 6 5 4 3 2 1 0
TTGE — TCIEU TCIEV — — TGIEB TGIEA
Initial value : 0 1 0 0 0 0 0 0
R/W : R/W — R/W R/W — — R/W R/W
The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for
each channel. The TPU has six TIER registers, one for each channel. The TIER registers are
initialized to H'40 by a reset and in hardware standby mode.
Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D
conversion start requests by TGRA input capture/compare match.
Bit 7
TTGE Description
0 A/D conversion start request generation disabled (Initial value)
1 A/D conversion start request generation enabled
Bit 6—Reserved: This bit cannot be modified and is always read as 1.
Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by
the TCFU bit when the TCFU bit in TSR is set to 1 in channels 1 and 2.
In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified.