Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 133 of 980
REJ09B0050-0600
6.3.7 Bus Control Register (BCR)
BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling
or disabling of the write data buffer function, and enabling or disabling of WAIT pin input.
Bit Bit Name Initial Value R/W Description
15 BRLE 0 R/W External Bus Release Enable
Enables or disables external bus release.
0: External bus release disabled
BREQ, BACK, and BREQO pins can be used
as I/O ports
1: External bus release enabled
14 BREQOE 0 R/W BREQO Pin Enable
Controls outputting the bus request signal
(BREQO) to the external bus master in the
external bus released state, when an internal
bus master performs an external address space
access, or when a refresh request is generated.
0: BREQO output disabled
BREQO pin can be used as I/O port
1: BREQO output enabled
13 − 0 R/W Reserved
Though this bit can be read from or written to,
the write value should always be 0.
12 IDLC 1 R/W Idle Cycle State Number Select
Specifies the number of states in the idle cycle
set by ICIS2, ICIS1, and ICIS0.
0: Idle cycle comprises 1 state
1: Idle cycle comprises 2 states
11 ICIS1 1 R/W Idle Cycle Insert 1
When consecutive external read cycles are
performed in different areas, an idle cycle can be
inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted