Datasheet

Section 23 Clock Pulse Generator
Rev.7.00 Mar. 18, 2009 page 955 of 1136
REJ09B0109-0700
Section 23 Clock Pulse Generator
This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (φ) and
internal clocks.
The clock pulse generator consists of an oscillator circuit, PLL circuit, and divider.
Figure 23.1 shows a block diagram of the clock pulse generator.
EXTAL
PLL circuit
(×1, 2, 4)
Oscillator
Divider
System clock
to φ pin
Internal clock
to peripheral
modules
SCK2 to SCK0
SCKCR
STC0, STC1
PLLCR
XTAL
Legend:
PLLCR: PLL system control register
SCKCR: System clock control register
Figure 23.1 Block Diagram of Clock Pulse Generator
The frequency can be changed by means of the PLL circuit. Frequency changes are made by
software by means of settings in the PLL control register (PLLCR) and the system clock control
register (SCKCR).
23.1 Register Descriptions
The clock pulse generator has the following registers.
• System clock control register (SCKCR)
• PLL control register (PLLCR)
23.1.1 System Clock Control Register (SCKCR)
SCKCR controls
φ clock output and selects operation when the frequency multiplication factor
used by the PLL circuit is changed, and the division ratio used by the divider.
CPG0400A_010020020400