Datasheet

Section 23 Clock Pulse Generator
Rev.7.00 Mar. 18, 2009 page 956 of 1136
REJ09B0109-0700
Bit Bit Name Initial Value R/W Description
7 PSTOP 0 R/W
φ Clock Output Disable
Controls
φ output.
Normal Operation
0:
φ output
1: Fixed high
Sleep Mode
0:
φ output
1: Fixed high
Software Standby Mode
0: Fixed high
1: Fixed high
Hardware Standby Mode
0: High impedance
1: High impedance
All module clock stop mode
0:
φ output
1: Fixed high
6 — 0 R/W Reserved
The initial value should not be changed.
5, 4 — All 0 R/W Reserved
These bits can be read from or written to. However,
the write value should always be 0.
3 STCS 0 R/W Frequency Multiplication Factor Switching Mode
Select
Selects the operation when the PLL circuit
frequency multiplication factor is changed.
0: Specified multiplication factor is valid after
transition to software standby mode
1: Specified multiplication factor is valid
immediately after STC1 and STC0 bits are
rewritten