Datasheet

Section 23 Clock Pulse Generator
Rev.7.00 Mar. 18, 2009 page 957 of 1136
REJ09B0109-0700
Bit Bit Name Initial Value R/W Description
2
1
0
SCK2
SCK1
SCK0
0
0
0
R/W
R/W
R/W
System Clock Select 2 to 0
Select the division ratio.
000: 1/1
001: 1/2
010: 1/4
011: 1/8
100: Setting prohibited
101: Setting prohibited
11×: Setting prohibited
Legend:
×: Don’t care
23.1.2 PLL Control Register (PLLCR)
PLLCR sets the frequency multiplication factor used by the PLL circuit.
Bit Bit Name Initial Value R/W Description
7
to
4
— All 0 — Reserved
These bits are always read as 0 and cannot be
modified.
3 — 0 R/W Reserved
This bit can be read from or written to. However,
the write value should always be 0.
2 — 0 — Reserved
This bit is always read as 0 and cannot be
modified.
1
0
STC1
STC0
0
0
R/W
R/W
Frequency Multiplication Factor
The STC bits specify the frequency multiplication
factor used by the PLL circuit.
00: × 1
01: × 2
10: × 4
11: Setting prohibited