Datasheet

Section 24 Power-Down Modes
Rev.7.00 Mar. 18, 2009 page 970 of 1136
REJ09B0109-0700
24.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)
MSTPCR performs module stop mode control.
Setting a bit to 1, the corresponding module enters module stop mode, while clearing the bit to 0
clears the module stop mode.
• MSTPCRH
Bit Bit Name Initial Value R/W Module
15 ACSE 0 R/W All-Module-Clocks-Stop Mode Enable
Enables or disables all-module-clocks-stop mode,
in which, when the CPU executes a SLEEP
instruction after module stop mode has been set for
all the on-chip peripheral functions controlled by
MSTPCR or the on-chip peripheral functions except
the TMR.
0: All-module-clocks-stop mode disabled
1: All-module-clocks-stop mode enabled
14 MSTP14 0 R/W EXDMA controller (EXDMAC)
*
13 MSTP13 0 R/W DMA controller (DMAC)
*
12 MSTP12 0 R/W Data transfer controller (DTC)
11 MSTP11 1 R/W 16-bit timer-pulse unit (TPU)
10 MSTP10 1 R/W Programmable pulse generator (PPG)
*
9 MSTP9 1 R/W D/A converter (channels 0 and 1)
8 MSTP8 1 R/W D/A converter (channels 2 and 3)
Note: * Not supported by the H8S2375, H8S/2575R, H8S/2373, and H8S/2373R.