Datasheet

Section 24 Power-Down Modes

Rev.7.00 Mar. 18, 2009 page 976 of 1136

REJ09B0109-0700

Oscillator

NMI

NMIEG

SSBY

NMI exception

handling

NMIEG=1

SSBY=1

SLEEP instruction

Software standby mode

(power-down mode)

Oscillation

stabilization

time t

OSC2

NMI exception

handling

Figure 24.2 Software Standby Mode Application Example

24.2.4 Hardware Standby Mode

Transition to Hardware Standby Mode: When the STBY pin is driven low, a transition is made

to hardware standby mode from any mode.

In hardware standby mode, all functions enter the reset state and stop operation, resulting in a

significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip

RAM data is retained. I/O ports are set to the high-impedance state.

In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before

driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while this

LSI is in hardware standby mode.