Datasheet

Section 24 Power-Down Modes
Rev.7.00 Mar. 18, 2009 page 980 of 1136
REJ09B0109-0700
24.4.3 EXDMAC, DMAC, and DTC Module Stop
Depending on the operating status of the EXDMAC, DMAC, or DTC, the MSTP14 to MSTP13
and may not be set to 1. Setting of the EXDMAC, DMAC, or DTC module stop mode should be
carried out only when the respective module is not activated.
For details, refer to section 8, EXDMA Controller (EXDMAC), section 7, DMA Controller
(DMAC), and section 9, Data Transfer Controller (DTC).
Note: The EXDMAC is not supported by the H8S/2375, H8S/2375R, H8S/2373, and
H8S/2373R.
24.4.4 On-Chip Peripheral Module Interrupts
Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module
stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU
interrupt source or the DMAC or DTC activation source.
Interrupts should therefore be disabled before entering module stop mode.
Note: The EXDMAC is not supported by the H8S/2375, H8S/2375R, H8S/2373, and
H8S/2373R
24.4.5 Writing to MSTPCR, EXMSTPCR
MSTPCR and EXMSTPCR should only be written to by the CPU.
24.4.6 Notes on Clock Division Mode
The following points should be noted in clock division mode.
• Select the clock division ratio specified by the SCK2 to SCK0 bits so that the frequency of φ is
within the operation guaranteed range of clock cycle time tcyc shown in the Electrical
Characteristics. In other words, the range of φ must be specified to 8 MHz (min); outside of
this range (φ < 8 MHz) must be prevented.
• All the on-chip peripheral modules operate on the φ. Therefore, note that the time processing
of modules such as a timer and SCI differ before and after changing the clock division ratio. In
addition, wait time for clearing software standby mode differs by changing the clock division
ratio.
• Note that the frequency of φ will be changed by changing the clock division ratio.