Datasheet

Section 25 List of Registers
Rev.7.00 Mar. 18, 2009 page 1006 of 1136
REJ09B0109-0700
Register
Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
TGRA_1 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TPU_1
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TGRB_1 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TCR_2 ⎯ CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_2
TMDR_2 ⎯ ⎯ ⎯ ⎯ MD3 MD2 MD1 MD0
TIOR_2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
TIER_2 TTGE ⎯ TCIEU TCIEV ⎯ ⎯ TGIEB TGIEA
TSR_2 TCFD ⎯ TCFU TCFV ⎯ ⎯ TGFB TGFA
TCNT_2 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TGRA_2 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TGRB_2 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Notes: 1. Loaded in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as
register information, and 16 bits otherwise.
2. For short address mode
3. For full address mode
4. For normal mode
5. For smart card interface mode
6. If the pulse output group 2 and pulse output group 3 output triggers are the same
according to the PCR setting, the NDRH address will be H'FF4C, and if different, the
address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C.
Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the
same according to the PCR setting, the NDRL address will be H'FF4D, and if different,
the address of NDRL for group 0 will be H'FF4F, and that for group 1 will be H'FF4D.
7. Not supported by the H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R.
8. Supported only by the H8S/2378 0.18μm F-ZTAT Group and H8S/2378R 0.18μm
F-ZTAT Group.