Datasheet

Section 26 Electrical Characteristics
Rev.7.00 Mar. 18, 2009 page 1080 of 1136
REJ09B0109-0700
Tp
t
AD
t
AD
t
AS2
t
AH2
t
CSD2
t
PCH1
t
AS3
t
CSD3
t
CASD1
t
AH3
t
CASD2
t
CASW2
t
AC2
t
AA5
t
AC7
t
WRD2
t
WDD
t
WDS2
t
WDH3
t
WCS2
t
WCH2
t
RDH2
t
OED2
t
OED1
φ
A23 to A0
RAS5 to RAS2
UCAS
LCAS
OE, RD
HWR
D15 to D0
OE, RD
HWR
D15 to D0
AS
Tr Tc1 Tc2
Tc3
Write
Read
DACK and EDACK timing: when DDS = 0 and EDDS = 0
RAS timing: when RAST = 0
Note:
DACK0, DACK1
EDACK2, EDACK3
t
DACD1
t
DACD2
t
EDACD1
t
EDACD2
t
WRD2
t
RDS2
Figure 26.17 DRAM Access Timing: Three-State Access (RAST = 1)