Datasheet

Section 26 Electrical Characteristics
Rev.7.00 Mar. 18, 2009 page 1081 of 1136
REJ09B0109-0700
Tp Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3
φ
A23 to A0
RAS5 to RAS0
UCAS
LCAS
OE, RD
HWR
D15 to D0
OE, RD
HWR
t
RCH
t
RCS2
t
AC8
t
CPW2
D15 to D0
AS
Read
Write
DACK and EDACK timing: when DDS = 1 and EDDS = 1
RAS timing: when RAST = 1
Note:
DACK0, DACK1
EDACK2, EDACK3
Figure 26.18 DRAM Access Timing: Three-State Burst Access