Datasheet

Appendix
Rev.7.00 Mar. 18, 2009 page 1104 of 1136
REJ09B0109-0700
Port Name
MCU Operating
Mode
Reset
Hardware
Standby
Mode
Software
Standby Mode
Bus Release
State
Program
Execution
State Sleep
Mode
PH1/CS5/
SDRAMφ
*
1
1, 2, 4, 7 [DCTL = 1]
Clock output
[DCTL = 0]
T
[DCTL = 1]
L
[DCTL = 0]
T
[DCTL = 1]
L
[DCTL = 0,
OPE = 0
CS output]
T
[DCTL = 0,
OPE = 1
CS output]
H
[Other than the
above]
keep
[DCTL = 1]
Clock output
[DCTL = 0,
CS output]
T
[Other than the
above]
keep
[DCTL = 1]
Clock output
[DCTL = 0,
CS output]
CS
[Other than the
above]
I/O port
PH0/CS4 1, 2, 4, 7 T T [OPE = 0,
CS output]
T
[OPE = 1,
CS output]
H
[Other than the
above]
keep
[CS output]
T
[Other than the
above]
keep
[CS output]
CS
[Other than the
above]
I/O port
WDTOVF 1, 2, 4, 7 H H H H H
*
3
Legend:
L: Low level
H: High level
keep: Input port becomes high-impedance, output port retains state
T: High impedance
DDR: Data direction register
OPE: Output port enable
Notes: 1. Not supported by the H8S/2378 Group.
2. Supported by the H8S/2378 0.18μm F-ZTAT Group and H8S/2378R 0.18μm F-ZTAT
Group only.
3. Low output if a watchdog overflow occurs when WT/IT is set to 1.