Datasheet

Rev.7.00 Mar. 18, 2009 page xi of lxvi
REJ09B0109-0700
Item Page Revision (See Manual for Details)
10.12.5 Pin Functions 523 Table amended
PDnDDR — 0 1 —
Pin function Data I/O PDn input PDn output Data I/O
Legend added
Legend: n = 7 to 0
10.13.5 Pin Functions 527 Table amended
PEnDDR 0 1 — 0 1 0 1 —
Pin function PEn
input
PEn
output
Data I/O PEn
input
PEn
output
PEn
input
PEn
output
Data I/O
Legend added
Legend: n = 7 to 0
10.14.4 Pin Functions
• PF7/φ
531 Table amended
PF7DDR 0 1
10.16.1 Port H Data
Direction Register
(PHDDR)
541 Table amended
Bit Bit Name Initial Value R/W Description
3 PH3DDR 0
W
2 PH2DDR 0
W
1 PH1DDR 0
W
0 PH0DDR 0 W
• Mode 7 (when EXPE = 0)
Pins PH3 to PH0 are I/O ports, and their functions can be switched with
PHDDR.
Pin PH1 functions as the SDRAMφ
*
1
output pin when the input level of the
DCTL pin
*
2
is high. When the input level of the DCTL pin
*
2
is low, pin
PH1 is an I/O port and its function can be switched with PHD
DR.
15.3.7 Serial Status
Register (SSR)
Normal Serial
Communication
Interface Mode (When
SMIF in SCMR is 0)
705 Note amended
Note: * Only 0 can be written, to clear the flag. Alternately,
use the bit clear instruction to clear the flag.
Smart Card Interface
Mode (When SMIF in
SCMR is 1)
709 Note amended
Note: 1. Only 0 can be written, to clear the flag. Alternately,
use the bit clear instruction to clear the flag.
2. Elementary time unit (etu): Transfer duration for one
bit