Datasheet

Rev.7.00 Mar. 18, 2009 page xx of lxvi
REJ09B0109-0700
Item Page Revision (See Manual for Details)
26.3.2 DC
Characteristics
Table 26.28 DC
Characteristics
1051 Table amended
Item Symbol Min. Typ. Max. Unit
Test
Conditions
Input high
voltage
STBY,
MD2 to MD0
V
IH
V
CC
× 0.9 — V
CC
+ 0.3 V
RES, NMI, EMLE V
CC
× 0.9 — V
CC
+ 0.3 V
EXTAL V
CC
× 0.7 — V
CC
+0.3 V
Port 3,
P50 to P53
*
3
,
ports 6
*
3
and 8
*
3
,
ports A to H
*
3
2.2 — V
CC
+0.3 V
Port 4, Port 9 2.2 — AV
CC
+0.3 V
Input low
voltage
RES, STBY,
MD2 to MD0,
EMLE
V
IL
–0.3 — V
CC
× 0.1 V
NMI, EXTAL –0.3 — V
CC
× 0.2 V
Ports 3 to 6
*
3
,
Port 8
*
3
,
ports A to H
*
3
,
port 9
–0.3 — V
CC
× 0.2 V
Output high All output pins V
OH
V
CC
–0.5 — V I
OH
= –200 μA
voltage
V
CC
–1.0 —
—
— V I
OH
= –1 mA
All output pins V
OL
— — 0.4 V I
OL
= 1.6 mA Output low
voltage
P32 to P35
*
4
— — 0.5 V I
OL
= 8.0 mA
Table 26.30
Permissible Output
Currents
1053 Table amended
Item Symbol Min. Typ. Max. Unit
SCL0, 1, SDA0, 1 I
OL
— — 8.0 mA <ermissible output low
current (per pin)
Output pins other
than the above
— — 2.0
26.3.3 AC
Characteristics
Table 26.34 Bus
Timing (2)
1059 Table amended
Item Symbol Min.
WAIT hold time t
WTH
5
26.4.3 Bus Timing
Figure 26.7 Basic Bus
Timing: Two-State
Access
1070 Figure amended
EDACK2, EDACK3
t
EDACD1
t
EDACD2
Figure 26.8 Basic Bus
Timing: Three-State
Access
1071 Figure amended
EDACK2, EDACK3
t
EDACD1
t
EDACD2
Figure 26.10 Basic
Bus Timing: Two-State
Access (CS Assertion
Period Extended)
1073 Figure amended
EDACK2, EDACK3
t
EDACD1
t
EDACD2