Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 206 of 1136
REJ09B0109-0700
⎯ a refresh operation is initiated in the RAS down state
⎯ self-refreshing is performed
⎯ the chip enters software standby mode
⎯ the external bus is released
⎯ the RCDM bit or BE bit is cleared to 0
If a transition is made to the all-module-clocks-stopped mode in the RAS down state, the clock
will stop with RAS low. To enter the all-module-clocks-stopped mode with RAS high, the
RCDM bit must be cleared to 0 before executing the SLEEP instruction.
Normal space
read
DRAM space
read
T
p
T
r
T
c1
T
c2
T
1
T
2
DRAM space read
T
c1
T
c2
Note: n = 2 to 5
RASn (CSn)
UCAS, LCAS
RD
OE
Data bus
A
ddress bus
φ
Row address Column address 1 Column address 2External address
Figure 6.32 Example of Operation Timing in RAS Down Mode
(RAST = 0, CAST = 0)