Datasheet

Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 215 of 1136
REJ09B0109-0700
When DDS = 0 or EDDS = 0: When DRAM space is accessed in DMAC or EXDMAC single
address transfer mode, full access (normal access) is always performed. With the DRAM interface,
the DACK or EDACK output goes low from the T
r
state.
In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used
when accessing DRAM space.
Figure 6.42 shows the DACK or EDACK output timing for the DRAM interface when DDS = 0 or
EDDS = 0.
T
p
RASn (CSn)
Read
Write
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
DACK or EDACK
Address bus
φ
T
r
T
c1
T
c2
Note: n = 2 to 5
T
c3
Row address Column address
High
High
Figure 6.42 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0
(RAST = 0, CAST = 1)